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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

Cadence Verification IP AppNotes Demonstrate the Use of Trace Files in Debugging

Cadence Verification IP (VIP) provides solutions for verifying compliance and compatibility…

• 4 min read
LFPS , Verification IP , Trace files , Denali to Cadence Migration , debug , PureSpec , VIP , PCIE2.0 , Application Notes , Appnotes , USB3.0 , Low Frequency Periodic Signaling , SuperSpeed USB Inter-Chip , debugging , SSIC

SoC and IP

M-PCIe—The New Big Thing from MIPI Alliance and PCI-SIG

If you’re reading this, you must have heard about the M-PCIe specification that has…

• 3 min read
controller IP , Intel , PCI Developers Conference , Design IP , IP , MIPI Alliance , cadence , Jacek Duda , controller , PHY , MIPI , M-PCIe , Arif Khan , SoC , Warsaw , future of IP , semiconductor IP , SoC Realization , PCI , M-PHY , PCI-SIG , 2013

System, PCB, & Package Design 

What's Good About FSP’s Schematic Generation? 16.6 Has Many New Enhancements!

The 16.6 release of Allegro FPGA System Planner (FSP) has MANY new enhancements in…

• 4 min read
Allegro 16.6 , cadence , FPGA-PCB Co-Design , FPGA System Planner , 16.6 , FPGAs , Design Entry HDL , component browser , symbol , design , Grzenia , Librarians , library , Schematic , FPGA , FPGA: PCB

Verification

How-To AppNotes on Cadence Palladium-XP Help Users Get the Basics Right

In simulation acceleration, there are multiple reasons for using gate-level netlists…

• 3 min read
Acceleration , netlist files , Palladium , LSF , Palladium XP , Emulation , Simulation acceleration , Cadence Application Notes , Compute server , Load Sharing Facility

System, PCB, & Package Design 

What's Good About Capture’s Find Command? 16.6 has a few new enhancements!

The 16.6 release of Alelgro Design Entry CIS (Capture) has added productivity enhancements…

• 1 min read
capture , Cadence Design Systems , Allegro 16.6 , Design Entry CIS , cadence , Find command , OrCAD Capture , 16.6 , Capture CIS , hierarchical schematics , SPB , Find result , design , OrCAD , Design Entry , Grzenia , PCB Capture , Schematic , Allegro

Verification

The Art of Modeling in e

Verification is the art of modeling complex relationships and behaviors. Effective…

• 4 min read
AF , Specman , Incisive , e language , Funcional Verification , coverage driven verification (CDV) , Modeling

Analog/Custom Design

OpenAccess (OA) Based Flow - Efficient Implementation of Mixed-Signal Design for…

I had the great opportunity to represent Cadence at the Design Automation Conference…

• 2 min read
Solutions , DAC , cadence , Analog-Centric , Austin , Open Access , analog , VDI , Digital-Centric , Virtuoso , digital , oa , Encounter Digital Implementation , mixed signal , Texas Instruments , Mixed-Signal Methodology Book

Verification

Rapid Adoption Kit (RAK) -- Creating UVM Verification Environments with Hardware…

The hands-on, learning-by-doing, trying, discovering, failing and learning approach…

• 2 min read
Palladium-XP , RAK , hardware assisted verification , Palladium XP , UVM Acceleration , Simulation acceleration , Cadence Hardware Acceleration , System Level Design Verification , Rapid Adoption Kits , RAKs

SoC and IP

Cadence First to Demo Complete M-PCIe PHY and Controller Solution at MIPI and PCI…

One of the hottest (or should I say coolest – because low power is so important)…

• 3 min read
Intel , PCI Developers Conference , Design IP , IP , Gen3 , cadence , LeCroy , controller , PHY , DevCon , MIPI , M-PCIe , PMC , Arif Khan , PCIe , semiconductor IP , PCI , PCI Express , M-PHY , 2013

Verification

Forte and Cadence at DAC: How to Deploy High-Level Synthesis

It's no secret that the transition to high-level synthesis (HLS) has historically…

• 2 min read
High-Level Synthesis , Mark Warren , DAC , C-to-Silcon Compiler , Mike Meredith , Jack Erickson , Cadence Theater , DAC 2013 , Brett Cline , Forte Cynthesizer , SystemC , HLS , ESL , C/C++

System, PCB, & Package Design 

What's Good About DEHDL’s Hierarchical Split Symbols? The Secret's in the 16.6 Release

The complexity of the designs is constantly increasing and more and more logic is…

• 2 min read
PCB , split symbols , Allegro Design Entry , hierarchy , Allegro 16.6 , cadence , DEHDL , symbol editor , 16.6 , Library flow , hierarchical schematics , Library and design data management , Design Entry HDL , hierarchical split symbols , design , PCB design , Design Entry , Grzenia , Librarians , ConceptHDL , library , Schematic

System, PCB, & Package Design 

Catch, Correct, and Prevent Common Package Design Errors with the 16.6 Cadence APD…

Designing an IC package substrate is a complex task. From picking the right materials…

• 3 min read
stacked dies , SiP , IC Package , IC Packaging , Digital SiP design , 16.6 , IC Packaging and SiP , APD , wirebonds , IC Packaging & SiP design , Allegro Package Designer , IC packaging documentation , APD 16.6 , SiP Layout , wirebonding , wirebond profile library , IC Package Physical layout and co-design

SoC and IP

MIPI Alliance Meeting Reflects the Rapid Growth of the Mobile Market

Let me start this entry on a bit of a personal note. As a Pole, I was very happy…

• 3 min read
controller IP , Design IP , IP , MIPI Alliance , D-PHY , Jacek Duda , BIF , Slimbus , IP integration , MIPI , CSI , Rick Wietfeldt , USB-IF , DSI , SoC , broadcom , Warsaw , future of IP , Evatronix , Qualcomm , SoC Realization , PCI Express , M-PHY , PCI-SIG

System, PCB, & Package Design 

Simultaneous Switching Noise Analysis – The Earlier the Better

The evolution of signal integrity analysis is similar to many electronic design tasks…

• 2 min read
PCB , electronics design , signal integrity analysis , Signal Integrity , PCB design , Sigrity , Allegro PCB Editor , SI analysis and modeling , Allegro

Analog/Custom Design

SKILL for the Skilled: The Partial Predicate Problem

The partial predicate problem describes the type of problem encountered when a function…

• 6 min read
Team SKILL , programming , Jim Newton , IC615 , SKILL for the Skilled , continuation passing , partial predicate , CPS , Lisp , SKILL++ , SKILL

Verification

Developing the Skill Set Required for SystemC TLM-Based Hardware Design and Veri…

I've written a lot about the benefits of moving hardware design and verification…

• 4 min read
time-to-market , High-Level Synthesis , transaction-level modeling , verification turnaround , TLM , Cadence Academic Network , university software program , RTL , System Design and Verification , C , rtl compiler , C-to-Silicon , metric-driven verification , SystemC , HLS , IEDEC , C++ , ESL

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Net Groups? See for Yourself in 16.6!

Just a brief blog today about a new feature in Allegro PCB Editor. A new net grouping…

• less than a min read
PCB , PCB Layout and routing , Constraint-driven PCB Design flow , Allegro 16.6 , cadence , 16.6 , Constraint Manager , Layout , design , "PCB design" , PCB design , Constraints , Grzenia , net groups , Allegro PCB Editor , NetGroup , Allegro

Analog/Custom Design

Virtuosity: 10 Things I Learned in May by Browsing Cadence Online Support

May was a big month for new videos. It was also a month that saw the release of Virtuoso…

• 1 min read
VLS GXL , Virtuoso Layout Suite L , Virtuoso , VLS L , Virtuoso Layout Suite , Virtuoso Layout Suite GXL , VLS XL , Virtuoso Layout Suite XL

System, PCB, & Package Design 

What's Good About RF PCB and Agilent ADS Via Exchange? 16.6 Has Many New Enhancements

The 16.6 Allegro PCB Editor and the Agilent Advanced Design System (ADS) interface…

• 6 min read
PCB , PCB Layout and routing , RF , Allegro GUI , Allegro 16.6 , RF PCB , 16.6 routing , Agilent , via exchange , 16.6 , layer stacks , ADS , SPB , PCB Editor , Layout , via , via patterns , design , vias , PCB design , Grzenia , Allegro PCB Editor , Agilent ADS , Allegro
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