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Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis
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Blog - Post List
Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays - Training Different Networks Using Hierarchical CNN

In this week's Whiteboard Wednesdays video, Michelle Mao follows up on last week…

• less than a min read
Whiteboard Wednesdays , IP , Tensilica

Breakfast Bytes

DARPA: All Must Have Prizes

At CDNLive Boston, the invited keynote was by Dr. Bill Chappell of DARPA's Microsystems…

• 4 min read
CDNLive , cdnlive boston , robotics , autonoous vehicles , craft , microsystems technology office , darpa

Breakfast Bytes

Electronic Design Automation Handbook

Way back in 2006, Luciano Lavagno, Lou Scheffer, and Grant Martin, all then at Cadence…

• 4 min read
TCAD , Electronic Design Automation , system design , EDAC , Testing , implementation , Circuit Design , process design , Breakfast Bytes , verification , book

Breakfast Bytes

Facebook's Aquila Flies...and OpenCellular

In Barcelona in February I attended a "keynote' with Mark Zuckerberg which was actually…

• 4 min read
aquila , Facebook , opencellular , zuckerberg , internet.org

Breakfast Bytes

What’s for Breakfast? Preview September 12th to 16th (video)

https://youtu.be/eDeD0mg7D54 Monday: My review of Electronic Design Automation…

• less than a min read
CDNLive , palladium z1 , AMD , H.265 , IEEE 802.3 , cdnlive boston , Ethernet , Emulation , codec , netflix , h.264 , vp9 , video codec , darpa

Breakfast Bytes

Cadence's History with MIPI

I talked last week to Kevin Yee, Sachin Dhingra, and Moshik Rubin about the history…

• 6 min read
Automotive , MIPI , mipi devcon , mobile

Whiteboard Wednesdays

Whiteboard Wednesdays - Benefits of Cadence Hierarchical CNN Design

In this week's Whiteboard Wednesdays video, Michelle Mao talks about Cadence hierarchical…

• less than a min read
Whiteboard Wednesdays , IP , Tensilica , CNN

Breakfast Bytes

SiFive: a RISC-V Fabless Semiconductor Company

A couple of weeks ago I talked to Krste Asanović and Jack Kang of SiFive. Jack is…

• 3 min read
risc-v , fabless , sutter hill ventures , freedom unleashed , freedom everywhere , sifive , foundry

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? New Concurrent Team Design Capability (Reason 2…

Use teamwork to get off the critical path! When (not if) change happens or scope…

• 3 min read
Allegro 17.2 , Symphony , Real Time Design , PCB design , Why Move Up to 17.2

System, PCB, & Package Design 

Cadence Online Support — Empowering Learning! New Features from July 2016

Lots of documents are posted on Cadence Online Support on regular basis. Let us take…

• 2 min read
cadence online , "PCB design" , application note , Allegro

Breakfast Bytes

CDNLive Boston Overview

CDNLive Boston took place last week. It is really CDNLive East Coast, and there were…

• 6 min read
CDNLive , Power Integrity , cdnlive boston , Signal Integrity , Breakfast Bytes

Breakfast Bytes

RISC-V Gathering Momentum

I've been writing quite a bit about RISC-V (pronounced "risk five") since I think…

• 4 min read
krste asonovic , risc-v , codasip , NVIDIA , google , andes , cortus , Breakfast Bytes , sifive , hp enterprise

Breakfast Bytes

Happy Birthday, HP 12c—35 Years and Counting

Last year was the 50th anniversary of Moore's Law. One consequence of Moore's Law…

• 3 min read
hewlett-packard , hp 12c , CMOS , hp12c , calculator , Breakfast Bytes

Verification

DisplayPort 8K in Olympics 2020

If you’re anything like me, you’ve spent the last couple of weeks glued to the TV…

• 3 min read
Verification IP , VIP , DisplayPort , Design and Verification IP , Olympics

Breakfast Bytes

What’s for Breakfast? Preview September 6th to 9th (video)

https://youtu.be/lD8VFUNds7o Monday: Labor Day. Tuesday: CDNLive Boston. I…

• less than a min read
risc-v , acquila , CDNLive , MIPI , Power Integrity , open cellular , cdnlive boston , mipi devcon , Facebook , Signal Integrity , sifive

Breakfast Bytes

MIPI SoundWire

The MIPI Alliance exists to standardize widely used interfaces in mobile, such as…

• 3 min read
USB Type-C , MIPI SoundWire , MIPI , lightning , Soundwire , RealTek

Analog/Custom Design

Virtuoso Video Diary: Introducing WSP Manager

Are you an advanced node layout or CAD engineer trying to find a methodology for…

• 2 min read
Routing , WSP , Rapid Adoption Kit , Advanced Node , Virtuoso Video Diary , Custom IC Design , Virtuoso Layout Suite

Whiteboard Wednesdays

Whiteboard Wednesdays - Application-Optimized DDR PHYs

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty takes a closer look…

• less than a min read
Whiteboard Wednesdays , memory subsystems , memory IP , DDR IP , DDR PHY

System, PCB, & Package Design 

Sneak Peek: Discussion Topics for Signal and Power Integrity Expert Panel at CDNLive…

Who? Istvan Novak - senior principal engineer at Oracle Kevin Roselle -…

• 2 min read
Power Integrity , cdnlive boston , Signal Integrity , PCB design
CDNS - Fix Layout Hompage