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Corporate News

The Three-Layer Cake: The Foundation Behind Intelligent Engineering

Artificial intelligence is rapidly becoming the engine behind the next era of technology…

Corporate
• 7 min read
featured , infrastructure ai , agentic ai , Principled Simulation , physical ai

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform
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Blog - Post List
Latest blogs

SoC and IP

How to Create a Working IoT Sensor in One Month

Cadence and ARM have created an IoT IP reference sub-system that can speed system…

• less than a min read
sensor , IoT , ARM , IoT subsystem , IoT sensor

Whiteboard Wednesdays

Whiteboard Wednesdays—Optimizing Neural Networks

In this week's Whiteboard Wednesdays video, Chris Rowen discusses optimizing neural…

• less than a min read
Whiteboard Wednesdays , IP , Chris Rowen , high throughput , low energy , Tensilica , neural networks

System, PCB, & Package Design 

Cadence Sigrity SystemSI Technology Highlighted at CDNLive SV 2016

This year’s CDNLive Silicon Valley developer conference had more than 125 presentations…

• 1 min read
PCB SI , PCB , SI , PCB Signal and power integrity , Signal Integrity , PCB design , Sigrity

Breakfast Bytes

Pieter Vorenkamp and IP at Cadence

Pieter Vorenkamp is the new(ish) senior VP and general manager of the semiconductor…

• 2 min read
IP , Pieter Vorenkamp , Breakfast Bytes

Breakfast Bytes

An Steegen's Secrets of Semiconductor Scaling

If you were asked where in the world the most leading-edge semiconductor research…

• 3 min read
scaling , an steegen , imec , FinFET , ITC , power , Breakfast Bytes , silicon nanowire

Breakfast Bytes

Designing for the Cloud

At the recent GSA silicon summit, there was a panel session on designing for the…

• 4 min read
cloud , accelerator , gsa silicon summit , gsa , datacenter

Whiteboard Wednesdays

Whiteboard Wednesdays—Ubiquitous USB Interface Evolution

In this week's Whiteboard Wednesdays video, Arif Kahn details the evolution of the…

• less than a min read
Whiteboard Wednesdays , IP , USB Type-C , USB , Arif Kahn

Breakfast Bytes

Security for IoT Is a Requirement, Not a Choice

It is hard to attend any sort of meeting to do with semiconductors without hearing…

• 4 min read
security , IoT , Internet of Things , gsa , Breakfast Bytes

Verification

Why Do We Need a Verification Language?

This month, we celebrate the 20 th anniversary of Specman’s introduction to the public…

• 4 min read
Specman , e , Aspect Oriented Programming , yoav hollander , verification

Academic Network

What Was on Offer at European Test Symposium (ETS) 2016 in Amsterdam?

IEEE European Test Symposium (ETS) is the largest event in Europe committed to presenting…

• 2 min read
ets , Cadence Academic Network

Academic Network

Students From Tianjin University in China Visit Cadence Sophia

Back in May, Professor Gilles Jacquemod and 9 engineering students from Tianjin University…

• 1 min read
Cadence Academic Network

Breakfast Bytes

Gary Patton: What's Next? Markets and Technology

One of the keynotes at the imec technology forum last month was by Gary Patton, the…

• 3 min read
Automotive , IoT , imec , GlobalFoundries , Breakfast Bytes

SoC and IP

Can You See Me? Putting Neural Networks in Everyday Devices

Neural networks have become very popular today due to their use in leading-edge technology…

• 1 min read
CVPR , Chris Rowen , Computer Vision , Tensilica , neural networks , CNN , image processing

SoC and IP

The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016

PCI-SIG is a leading event in cloud infrastructure transformation, which is markets…

• 1 min read
PCIe Gen4 , 10G-KR , SerDes , PCI Express

Academic Network

CDNLive EMEA: An Intern's Perspective

CDNLive EMEA is often cited as the most exciting event of the year for Cadence. This…

• 3 min read
Cadence Academic Network , CDNLive EMEA

Breakfast Bytes

99.7% of Transistors Manufactured Are Memory

I was in Brussels a couple of weeks ago to attend imec's annual technology forum…

• 5 min read

Breakfast Bytes

RISC-V—Instruction Sets Want to Be Free

I had never heard of the RISC-V (pronounced five, not vee) instruction set until…

• 5 min read
risc-v , instruction set , krste asanovic , isa , RISC , UC Berkeley , instruction set architecture

Verification

IP Group @ 53rd DAC – Veni Vidi Vici

Another DAC, and this year someone put a jalapeno in my margarita at the Denali Party…

• 2 min read
DAC , Verification IP , IP , DDR4 , LPDDR4 , SerDes

Analog/Custom Design

Waveform Thumbnails

Wouldn't it be great if you could see your plots directly on the schematic? Well…

• 2 min read
Explorer , waveforms , waveform thumbnails
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