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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
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Blog - Post List
Latest blogs

Academic Network

EDA Summer Camp—Cadence Taiwan Hosts Top University Students

To help more students majoring in Electronics Engineering increase their understanding…

• 1 min read
Cadence Academic Network , academic workshop , academia , EDA

Verification

Making it Easier to Apply Palladium Z1 to SoC Performance Analysis

Recently, Renesas combined the Cadence® Interconnect Workbench, the Cadence vManager…

• 1 min read
Interconnect Workbench , customer feedback , success story , Palladium , Renesas

Analog/Custom Design

The Art of Analog Design: Part 3, Monte Carlo Sampling

In Part 2, we looked at Monte Carlo sampling methods. In Part 3, we will consider…

• 4 min read
Analog Design Environment , APS , ADE Explorer , Analog Simulation , analog , ADE , Monte Carlo , Analog Design Environment , ViVA , ADE Assembler , Cusstom IC Design

Breakfast Bytes

What's For Breakfast? Video Preview September 25th to 29th 2017

https://youtu.be/Uubpn09k83U Coming from Testarossa Winery, Los Gatos (camera…

• less than a min read
semi , business models , EDPS , sjsu , Jim Hogan , neural nets , smc

Analog/Custom Design

Virtuosity: Sweeping Multiple DSPF Views in ADE

Wouldn't it be great if you could have a view for your DSPF files and sweep them…

• 3 min read
Analog Design Environment , ViVa-XL , custom/analog , ADE Explorer , Analog Simulation , DSPF , ADE , Block-level simulation , Virtuoso Analog Design Environment , Analog Design Environment , Schematic Editor , ViVA , Virtuosity , Circuit Design , Custom IC Design , Schematic , ADE Assembler

Breakfast Bytes

Show Me the Money

I have put out some posts about generic business models and startups. However, if…

• 7 min read
investors , EDA , startups , Breakfast Bytes

Breakfast Bytes

Coincidence and Another Record

Record 1 I recently reached a sort of record that I detailed in my post The 500th…

• 6 min read
SIA , hock tan , gsa , Breakfast Bytes

The India Circuit

CDNLive India 2017: ThinCi on AI, Machine Learning and Deep Learning

Last week’s blog was about Venu Puvvada’s keynote at CDNLive India. Today’s blog…

• 4 min read
artificial intelligence , CDNLive India , deep learning , CDNLive , ThinCi , machine learning

Breakfast Bytes

India, Singapore, Hong Kong

What do India, Singapore, and Hong Kong have in common? Well, I visited them all…

• 8 min read
CDNLive , lee kuan yew , hong kong , sir john cowperthwaite , bangalore , Breakfast Bytes , India , Singapore

Whiteboard Wednesdays

Whiteboard Wednesdays - Implementation Challenges of Embedded Automatic Speech Recognition…

In this week’s Whiteboard Wednesdays, Raul Casas, systems architect IP group, talks…

• less than a min read
Whiteboard Wednesdays , Automatic Speech Recognition

SoC and IP

USB 3.2—The USB Type-C Connector Finally Met its Match

It’s only a week before the first event of USB Developer Days , a series of meetings…

• 1 min read
USB 3.0 , USB Type-C , DisplayPort , USB , USB 3.2 , power delivery , USB 3.1

Breakfast Bytes

CDNLive India 2017 Trip Report

I went to Bangalore to CDNLive India. It has a different structure from the other…

• 6 min read
ml , CDNLive India , dl , CDNLive , machinelearningdeeplearning , AI , Breakfast Bytes

Analog/Custom Design

Virtuosity: Sweeping Multiple Config Views

Before IC6.1.7 ISR10, you could sweep multiple views in ADE for only one block in…

• 2 min read
Analog Design Environment , ADE Explorer , Explorer , Analog Simulation , ADE , Virtuoso Analog Design Environment , Analog Design Environment , Schematic Editor , Virtuosity , Circuit Design , Custom IC Design , Schematic , ADE Assembler

System, PCB, & Package Design 

Follow Video-Embedded Troubleshooting Articles for Easier Debugging and Empowered…

Finding a way out of situations is routine in today’s ever changing world—more so…

• 2 min read
PCB , AMS simulator , OrCAD Capture , Allegro

Breakfast Bytes

Legato: Smooth Memory Design

At CDNLive in Bengaluru (fka Bangalore), Cadence announced the Legato solution for…

• 4 min read

Analog/Custom Design

Virtuosity: What Color is Your Virtuoso Wearing Today?

Like you, Virtuoso can dress in a different color too every day. Interested to know…

• 3 min read
Customize Virtuoso , Virtuoso Editor , color , color-aware design , Virtuosity , Custom IC

Breakfast Bytes

TSMC Process Roadmap Update

This Wednesday was TSMC's OIP Ecosystem Forum, one of two major events that TSMC…

• 5 min read
22_ULP , 22_ULL , 7nm+ , 12FFC , TSMC , 16FFC , 28HPC+ , 7nm , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview September 18th to 22nd 2017

https://youtu.be/mrUIXwMuNy8 Coming from TSMC OIP Symposium, Santa Clara (camera…

• less than a min read
legato , CDNLive , hong kong , neural nets , India , Singapore

Breakfast Bytes

Why Are Design Tools So Bad? Or Are They?

In a recent feature article at Electronic Engineering Journal, Kevin Morris asks…

• 6 min read
electronic engineering journal , bugs , EDA , design tools
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