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Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent

Corporate News

AI Infrastructure Starts Beyond the Chip

Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation…

Corporate
• 8 min read
chip , featured , AI infrastructure , agentic ai , packaging
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

Offtopic: Immersive Vincent van Gogh

Cadence has a global holiday tomorrow and Breakfast Bytes will not appear. Back on…

• 8 min read
offtopic , van gogh , immersive van gogh

System, PCB, & Package Design 

Welcome to the System Analysis Knowledge Bytes Blog Series

Welcome to the System Analysis Knowledge Bytes blog series! The first blog in this…

• 4 min read
Sigrity and Systems Analysis , Celsius Thermal Solver , Sigrity Aurora , Clarity 3D Transient Solver , Sigrity SPEED2000 , AMX , Sigrity Suite , Sigrity XcitePI , Sigrity Advanced PI , Sigrity PowerSI , Clarity 3D Layout , awr , Virtuoso RF Solution , Sigrity OptimizePI , Sigrity Broadband SPICE , AMX Planar 3D Solver , Sigrity XtractIM , Sigrity PowerDC , Clarity 3D Solver , Sigrity IBIS Modeling , Clarity 3D Workbench , Sigrity Advanced SI

カスタムIC／ミックスシグナル

Virtuosity: .simrc ファイルとネットリストのカスタマイズの裏側にある謎

ネットリスティングはデザインシミュレーションにおいて不可欠な部分です。ネットリストは、望ましいシミュレーション結果を達成するためにシミュレータにコネクティビティとマッピングの情報を伝えるために作成します…

• 1 min read
ic design methodology , AMS , Analog Design Environment , ic analog design , Cadence blogs , programming , mixed-signal simulators , custom/analog , Analog Simulation , analog , Mixed-Signal , full custom ic design , Virtuoso Analog Design Environment , Virtuoso , Spectre , Virtuosity , ICADVM20.1 , Circuit Design , mixed signal , analog design , japanese blog , Custom IC Design , IC6.1.8 , SKILL , Schematic , Analog IC Design , custom design technology , custom integrated circuit

Computational Fluid Dynamics

The CFD Vision 2030 Roadmap: 2020 Status, Progress, and Challenges

After a long writing (and longer editing and approval seeking) process, the AIAA…

• 2 min read
CFD , Numerical Algorithms , geometry modeling , Knowledge Extraction , Multidisciplinary , Computational Fluid Dynamics , optimization , visualization , CFD Vision 2030 , HPC , Mesh Generation , simulation

Breakfast Bytes

July Update

This is the July edition of the now monthly update post, with small updates to existing…

• 8 min read
ransomware , featured post , 6ghz , update , inmos , spectrum , GlobalFoundries , supply chain attack , newport wafer fab

Breakfast Bytes

Designed with Cadence Video Series

Designed with Cadence is a video series made with Cadence customers about how they…

• 1 min read
featured post , video , designed with cadence , dwc

Breakfast Bytes

HOT CHIPS 2021 Preview

As usual in August, it is HOT CHIPS. I always find this one of the most interesting…

• 4 min read
Intel , AMD , IBM , Samsung , hot chips , ARM

RF /マイクロ波設計

μWaveRiders:Cadence AWR Design Environment V16 ソフトウェアのリリースをハイライト

Team RF "μWaveRiders" ブログシリーズはCadence AWR RF製品のためのショーケースです。月ごとの話題はCadence AWR Design…

• less than a min read
microwave , RF Simulation , Circuit simulation , Analyst 3D FEM EM Simulator , RF design , AXIEM 3D Planar Simulator , japanese blog , awr v16 , AWR Design Environment release , Visual System Simulator(VSS)

Breakfast Bytes

Sunday Brunch Video for 25th July 2021

https://youtu.be/cwT7KL4iShY Made on "a tropical beach" Monday: Aerospace and Defense…

• less than a min read
sunday brunch

RF Engineering

μWaveRiders: Cadence AWR Design Environment V16 Software Release Highlights

The Cadence AWR Design Environment V16 production release is now available for download…

• 3 min read
RF Simulation , Circuit simulation , Analyst 3D FEM EM Simulator , RF design , AXIEM 3D Planar Simulator , microwave office , Visual System Simulator (VSS) , awr v16 , AWR Design Environment release

Computational Fluid Dynamics

This Week in CFD

Given that I'm perpetually late on sharing This Week in CFD here on the Cadence CFD…

• less than a min read
CFD , Marine Engineering , Pointwise , Computational Fluid Dynamics , fluid dynamics , Omnis

System, PCB, & Package Design 

BoardSurfers: Accelerating Allegro Layout Tools Using NVIDIA GPUs for Complex Board…

Boards and Packages are getting extremely complex and large; what used to be considered…

• 1 min read
Allegro Package Designer , Allegro PCB Editor

System, PCB, & Package Design 

BoardSurfers: Installation Know-How: Download Manager – Better than Ever Before

The Download Manager user interface has been revamped in 17.4-2019 HotFix 019. Various…

• 3 min read
Cadence Design Systems , Installation Know-How , 17.4 , BoardSurfers , Allegro OrCAD Installer , 17.4-2019 , Download Manager , OrCAD , installation , Allegro

Computational Fluid Dynamics

Damen: Wind Study On A Slender Boat Design Using Computational Fluid Dynamics

DAMEN and Numeca develop a CFD methodology to proof a vessel has sufficient transversal…

• 1 min read
naval archicture , Marine Engineering , Wind Study , fluid dynamics , IMO regulations , simulation software

Breakfast Bytes

Machine Learning in EDA

Yesterday, in my post Cerebrus: The Future of Intelligent Chip Design , I talked…

• 5 min read
featured post , xcelium ml , cerebrus , JasperGold , allegro x

System, PCB, & Package Design 

Cadence OrCAD and Allegro 17.4-2019 HotFix SPB17.40.019 is Now Available

The HotFix 019 (QIR 3, indicated as 2021.1 in the application splash screens) update…

• 6 min read
System Capture , 17.4 , OrCAD Capture , PSPICE , PCB Editor , EDM , Allegro Package Designer , 17.4-2019 , Topology Explorer , Allegro System Capture , Allegro PCB Editor , Pulse , 17.4-QIR3

Breakfast Bytes

Cadence Cerebrus - Intelligent Chip Explorer

This morning, we announced the Cadence Cerebrus Intelligent Chip Explorer, a machine…

• 5 min read
Genus , featured post , cerebrus , cloud , cadence cloud , Innovus , digital full flow , physical design , Synthesis , timing signoff

Life at Cadence

How Culture Can Flourish in the New Normal

Peter Drucker rightly said, “Culture eats strategy for breakfast”. An inclusive high…

• 5 min read
Culture

Breakfast Bytes

CadenceLIVE Cloud Panel

At the recent CadenceLIVE Americas, most of the sessions were pre-recorded with a…

• 11 min read
featured post , on-prem , cloud , cadencelive americas , cadence cloud , cadencelive
CDNS - Fix Layout Hompage