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Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent

Corporate News

AI Infrastructure Starts Beyond the Chip

Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation…

Corporate
• 8 min read
chip , featured , AI infrastructure , agentic ai , packaging
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

Gall's Law and Big Ball of Mud

Gall's Law says: A complex system that works is invariably found to have evolved…

• 4 min read
design patterns , software development

Analog/Custom Design

Virtuoso Video Diary: Incremental Simulations with Enhanced Reference Histories and…

Gone are the days of exporting results from multiple interactive runs and combining…

• 4 min read
Analog Design Environment , ICADVM18.1 , Analog Design Environment , Virtuosity , Virtuoso Video Diary , Custom IC , IC6.1.8 , Assembler , ADE Assembler

Spotlight Taiwan

RF/微波設計 隨選豐富影片信手拈來!

Cadence 團隊為客戶精選從去年至今年RF/微波設計一系列精采演講，內容涵蓋Cadence如何整合RF/微波設計的產品組合，提供市場上最全面的RF設計解決方案…

• less than a min read
5G , awr , EMX , taiwanese blog

Breakfast Bytes

Dynamic Duo 2: The Sequel

There's a story, probably apocryphal, about a screenwriter pitching a movie in Hollywood…

• 6 min read
dynamic duo , prototyping , protium x2 , palladium z2 , Emulation , FPGA prototyping , software development , firmware development

Computational Fluid Dynamics

This Week in CFD

It’s a good Friday for the latest roundup of CFD flotsam and jetsam from the ocean…

• less than a min read
CFD , Pointwise , Computational Fluid Dynamics

System, PCB, & Package Design 

ASCENT: Ready, Steady, Design ... Even With Existing Libraries

After a quick overview of Allegro® System Capture , let’s start at the very beginning…

• 3 min read
System Capture , 17.4 , cadence , logical design , Allegro Unified Libraries , 17.4-2019 , Front-end PCB design , logic-capture , PCB design , Allegro System Capture , ASCENT , Schematic , Allegro

Breakfast Bytes

Offtopic: Podcasts

Tomorrow is another Cadence global holiday. None of us will be working and Breakfast…

• 8 min read
offtopic , podcast

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: EMX Planar 3D Solverで受動素子と能動素子を持つRFブロックをシミュレートするには？

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
AXIEM , VLS EXL , EM Solver , Virtuoso Meets Maxwell , Electromagnetic analysis , black boxing , Virtuoso , EMX , ICADVM20.1 , japanese blog , Clarity 3D Solver , Virtuoso Layout Suite EXL

カスタムIC／ミックスシグナル

Start Your Engines: SimVision Mixed-Signal Debug Optionを使ってル・マンで優勝する

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により…

• less than a min read
AMS Designer , Start Your Engines , simvision , analog/mixed-signal , Virtuoso , AMSD Flex Mode , japanese blog , mixed-signal design , debugging , mixed-signal verification

Computational Fluid Dynamics

Resolving Boundary Layers with Unstructured Quad and Hex Meshing: On-Demand Webi…

All things being equal, CFD practitioners prefer to use hexahedral mesh cells in…

• less than a min read
CFD , Pointwise , Computational Fluid Dynamics

Breakfast Bytes

The First Commercial Computer Shipped 70 Years Ago Today

Today is the 70th anniversary of a very significant event in all our lives, even…

• 5 min read
first computer , univac

System, PCB, & Package Design 

(P)SpiceItUp: Generating ISO 7637-2 Standard Pulse 2a in PSpice A/D

Many times, you would have required to create a standard pulse waveform that can…

• 2 min read
17.4 , OrCAD Capture , PSpiceA/D , Capture CIS , (P)SpiceItUp , 17.4-2019 , OrCAD

Digital Design

Library Characterization Tidbits: Define Measurements to Suit Your Characterization…

Do you have a requirement to specify measurements that are not default while performing…

• 3 min read
memory characterization , define_measure , Liberate MX , Library Characterization Tidbit , Liberate Characterization Portfolio

定制IC芯片设计

Virtuoso Meets Maxwell：为什么没有提到引线键合IC？

当今的许多模拟，RF和混合信号设计都要求在同一模组内部集成多个不同工艺的IC，以实现所需的性能目标。设计师使用异构器件集成方法能够获得单片IC (SoC) 设计上不容易达到的结果…

• 1 min read
Chinese blog , ICADVM18.1 , Co-Design , Virtuoso System Design Environment , Virtuoso RF Solution , Wirebond , Electromagnetic analysis , Virtuoso , Custom IC Design , Allegro

Breakfast Bytes

Intel IDM 2.0

You've probably read in the press that Intel's new CEO, Pat Gelsinger, laid out his…

• 6 min read
Intel , icf , idm 2.0 , intel custom foundry , foundry

Analog/Custom Design

Spectre Tech Tips: Detecting Leakage Path Current Hotspots

In circuit design, wrong connectivity may cause undesired leakage paths that may…

• 2 min read
Dynamic design checks , Spectre design checks , leakage path detection , Spectre , dyn_dcpath , dyn_subcktpwr

Digital Design

Pegasus: Get Your Wings: Virtuoso/Pegasus In-Design Signoff

The beauty of Pegasus is that it doesn’t only work excellently in standalone mode…

• 2 min read
Pegasus Verification System , Interactive SignOff Fill , pegasus , Pegasus Interactive , Density analysis , design for manufacturing

Breakfast Bytes

Stopping Online Fraud

I attended a webcast on Anti-Fraud organized by the RSA Conference in the leadup…

• 6 min read
security , ransomware , rsa

Analog/Custom Design

Virtuoso Video Diary: Tabular Graph in Virtuoso Visualization and Analysis XL

Do you know you can now use Tabular Graph feature in Virtuoso Visualization and Analysis…

• 2 min read
Analog Design Environment , ViVa-XL , custom/analog , ADE Explorer , Analog Simulation , ADE , Virtuoso , ViVA , Virtuosity , Custom IC Design , ADE Assembler
CDNS - Fix Layout Hompage