Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA

Corporate News

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
• 8 min read
featured , physical ai , HGR , AI , Honda
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

Machine Learning in EDA

Yesterday, in my post Cerebrus: The Future of Intelligent Chip Design , I talked…

• 5 min read
featured post , xcelium ml , cerebrus , JasperGold , allegro x

System, PCB, & Package Design 

Cadence OrCAD and Allegro 17.4-2019 HotFix SPB17.40.019 is Now Available

The HotFix 019 (QIR 3, indicated as 2021.1 in the application splash screens) update…

• 6 min read
System Capture , 17.4 , OrCAD Capture , PSPICE , PCB Editor , EDM , Allegro Package Designer , 17.4-2019 , Topology Explorer , Allegro System Capture , Allegro PCB Editor , Pulse , 17.4-QIR3

Breakfast Bytes

Cadence Cerebrus - Intelligent Chip Explorer

This morning, we announced the Cadence Cerebrus Intelligent Chip Explorer, a machine…

• 5 min read
Genus , featured post , cerebrus , cloud , cadence cloud , Innovus , digital full flow , physical design , Synthesis , timing signoff

Life at Cadence

How Culture Can Flourish in the New Normal

Peter Drucker rightly said, “Culture eats strategy for breakfast”. An inclusive high…

• 5 min read
Culture

Breakfast Bytes

CadenceLIVE Cloud Panel

At the recent CadenceLIVE Americas, most of the sessions were pre-recorded with a…

• 11 min read
featured post , on-prem , cloud , cadencelive americas , cadence cloud , cadencelive

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: Cadence Learning and SupportポータルのVirtuoso RF Solutionプロダクト…

Virtuoso Meets Maxwell はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• 1 min read
VRF , Virtuoso Meets Maxwell , COS product page , Virtuoso RF Solution , Spectre , japanese blog , Clarity 3D Solver , Cadence Learning and Support portal , Custom IC Design , VMM

カスタムIC／ミックスシグナル

Virtuoso Video Diary: LSCSジョブ制御モード - クラウド・シミュレーションを実現

Virtuoso ADE Assembler はアナログやミックスシグナルの設計のためシミュレーションを実行する、信頼されたツールとなっています。しかし、大量のシミュレーションを行うような状況では…

• less than a min read
cloud simulations , Virtuoso ICADVM20.1 , ADE Explorer , custom IC simulation , ADE XL , cloud , ADE , Virtuoso Analog Design Environment , Virtuoso Video Diary , Virtuoso IC6.1.8 , large-scale simulations , japanese blog , Custom IC Design , ADE Assembler

Verification

Comprehensive Approach to Verification of Interconnect-Centric Systems

Many of today’s SoCs are built around multi-layered, sophisticated interconnect IP…

• 2 min read
interconnect , scoreboard , SoC verification , Functional Verification

Analog/Custom Design

Virtuosity: Making Optimum Use of Resources in Distributed Farm

Details on a dedicated tab "Resources" in Job Policy form, which helps to do resource…

• 4 min read
SGE , Analog Design Environment , LBS , Job Policy , ADE , LSF , Virtuoso , Virtuosity , distributed processing , Custom IC Design , IC6.1.8 , Assembler , ADE Assembler

Breakfast Bytes

75 Years of the Microprocessor

At the recent ISCA, there was a panel session with some of the major contributors…

• 7 min read
isca , microprocessor

Verification

Why IDE Security Technology for PCIe and CXL?

The new cloud, AI, Analytics, and Edge usage models with exponential data growth…

• 3 min read
Verification IP , Functional Verification , VIP , System Verification , simulation , verification

Breakfast Bytes

Aerospace and Defense Systems Day...and DAU

Coming up on July 28 is CadenceCONNECT Aerospace and Defense Systems Day. Cadence…

• 3 min read
A&D , featured post , Aerospace , eda101 , cadenceconnect , defense , dau

Breakfast Bytes

Sunday Brunch Video for 18th July 2021

https://youtu.be/nZ4lisR19nQ Made on my balcony (camera Carey Guo) Monday: Tesla…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

在云端运行 Clarity 3D Solver

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章“ Bringing Clarity to the…

• 1 min read
Chinese blog , Clarity 3D Solver Cloud , 云计算 , 电磁分析 , 中文 , 系统分析 , cadence cloud , 云 , EM , 混合云 , clarity

Computational Fluid Dynamics

This Week in CFD

Something weekend this way comes (to quote my online pal Brian who quotes Macbeth…

• 1 min read
CFD , Pointwise , Computational Fluid Dynamics , CFD Applications , NUMECA

Digital Design

Voltus Voice: Full-Chip Resistance Analysis – The Holy Grail of Power Grid Verif…

Do you want to determine the weak spots in your power grid network at the start of…

• 6 min read
Silicon Signoff and Verification , Voltus IC Power Integrity Solution , power grid , Least-Resistive Path , Power Integrity , resistance analysis , IR drop , Full-Chip

Breakfast Bytes

What Comes after 2nm GAA?

There are three companies that currently pursue the smallest geometries, what I've…

• 6 min read
forksheet , 3nm , imec , airgap , 2nm

System, PCB, & Package Design 

BoardSurfers: Exchanging Manufacturing Data in IPC-2581 Format Using Allegro PCB…

IPC-2581 ensures efficient PCB design data transfer and brings advanced capabilities…

• 6 min read
Cadence Design Systems , 17.4 , PCB manufacturing , Gerber , BoardSurfers , IPC , IPC-2581 Consortium , 17.4-2019 , PCB design , PCB data exchnage , Allegro PCB Editor , IPC-2581 , PCB standards , Allegro

Breakfast Bytes

AWR: Intelligent RF Design

There is a new release of the AWR Design Environment with cross-platform workflows…

• 4 min read
5G , RF , featured post , awr , RF design , awr v16 , radios
CDNS - Fix Layout Hompage