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Life at Cadence

Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
• 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
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Blog - Post List
Latest blogs

Verification

e Templates – Cool Tool, Now Even Cooler

One of the reasons why verification engineers love e is the power it gives them as…

• 3 min read

Breakfast Bytes

Andy Grove, RIP

Andy Grove, co-founder and long-time CEO of Intel, passed away on Monday. He was…

• 3 min read
Intel , only the paranoid survive , Fairchild , high output management , andy grove

Whiteboard Wednesdays

Whiteboard Wednesdays—Assertion-Based VIP

In this week's Whiteboard Wednesdays video, Tom Hackett takes a closer look at assertion…

• less than a min read
Verification IP , Whiteboard Wednesdays , IP , VIP , assertion-based VIP

SoC and IP

TSMC’s Technology Symposium 2016 is the Place to be for Innovation

At this year’s Technology Symposium, TSMC disclosed that they will provide two N7…

• less than a min read
DDR4 , LPDDR4 , TSMC Tech Symposium , ip cores , PCIe , 16FF+

Breakfast Bytes

EDPS: Dolphins and FinFETs

The Electronic Design Process Symposium (EDPS) has been held in late April or early…

• 3 min read
Low Power , Electronic Design Process , multi-die , Monterey , EDPS , cyber security

Academic Network

Stratus High-Level Synthesis Is Available to Academia

To support academia using the latest industry-standard tools, Cadence's Stratus High…

• 1 min read
Cadence Academic Network , academia , Stratus , HLS

Breakfast Bytes

TSMC Technology Symposium: Process Status

At the recent TSMC Technology Symposium, various speakers gave details of the various…

• 6 min read
Automotive , specialty processes , IoT , TSMC , <7nm , InFO , 16FFC , n7 , n10 , Breakfast Bytes , 16FF+

Academic Network

Tensilica Day in Hanover

The idea to have a Tensilica Day at University of Hanover was born during CDNLive…

• 2 min read
Cadence Academic Network , Tensilica

SoC and IP

DDR/LPDDR 4/3 Combo PHY in TSMC 28HPC Silicon Proven at 2400 Mbps

Back in October we announced the TSMC 28HPC tapeout of our DDR/LPDDR 4/3 Combo PHY…

• 1 min read

Breakfast Bytes

TSMC Technology Symposium: Four Strategic Markets

When Willie Sutton was asked by the judge why he kept robbing banks, he said "because…

• 3 min read
Automotive , IoT , TSMC , TSMC Technology Symposium , 7ff , 16ff , 10FF , 16nm , HPC , n7 , mobile , n10 , 7nm , 10nm , n16

Breakfast Bytes

Dark Silicon: Not a Character from Star Wars

Dark Silicon may sound like a character from the latest Star Wars movie, but it actually…

• 6 min read
Dennard scaling , Dark Silicon , moore's law , dennard , multicore

Breakfast Bytes

EDAC Becomes...You Have to Be There to Be the First to Know

When Bob Smith took over as the Executive Director of EDAC, I called him up and one…

• 2 min read
bob smith , EDA Consortium , EDAC , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays—Implementation of Higher Speed PCIe Gen4 IP

In this week's Whiteboard Wednesday's video, Gopi Krishnamurthy highlights how Cadence…

• less than a min read
Whiteboard Wednesdays , IP , PCIe Gen4 , PHY IP , PCIe , PCI Express

Breakfast Bytes

The Economist on the End of Moore's Law

"The number of people predicting the end of Moore's Law doubles every two years.…

• 3 min read
Intel , The Economist , moore's law , FinFET

Breakfast Bytes

A Brief History of Cadence: The Solomon-Costello Era

Cadence has grown from a small startup to a $1.7B corporation. Its history includes…

• 3 min read
Jim Solomon , ECAD , Joe Costello , SDA

System, PCB, & Package Design 

Designing a New Component from Scratch Inside Your Layout Environment

Have you ever needed to build a component with a custom, complex pin pattern? Have…

• 6 min read
IC package design , APD , package design , Allegro Package Designer , SiP Layout , substrate design tools

Breakfast Bytes

Tensilica Has Its Own Track at CDNLive Silicon Valley

Tensilica products are a bigger business than many people realize. The product line…

• 2 min read
IP , CDNLive , processor , Tensilica , Xtensa , DSPs

Breakfast Bytes

DVCon Keynote: the Past and Future of Verification

Last week was DVCon, the design and verification conference. Despite the D standing…

• 5 min read
SystemVerilog , Wally Rhines , formal , Verilog , Emulation , DVcon , Rhines , simulation , verification

Breakfast Bytes

EDA in the Cloud: Stormy Weather

SoC design groups don't do clouds. True, they take advantage of some of the underlying…

• 4 min read
security , EDA , cloud , Breakfast Bytes , cloud computing
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