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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
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Blog - Post List
Latest blogs

SoC and IP

PCI Express Trends and News at PCI-SIG 2016

PCI-SIG Developers Conference 2016 is now history, taking place at the Santa Clara…

• 1 min read
PCIe Gen4 , 10G-KR , SerDes , PCI Express

Breakfast Bytes

Softbank Buys ARM for $32B

Over the weekend it seems that Softbank has closed a deal to acquire ARM Holdings…

• 4 min read
softbank , Mobile World Congress , ARM , sprint

Breakfast Bytes

The Future of Neural Networks...and Our Robot Overlords

Chris Rowen, the CTO of the Cadence IP group, wrapped up the recent seminar in Las…

• 4 min read
open datasets , training , neural networks , data scientist , privacy , CNN , Breakfast Bytes

Academic Network

Meet the Winners of Tensilica Xtensa Embedded DSP Design Contest India 2016

The winners of the Tensilica Xtensa Embedded DSP Design Contest have been announced…

• 1 min read
Cadence Academic Network , Bangladesh , Tensilica , Xtensa Design Contest , India

Breakfast Bytes

Hierarchical Neural Networks

The German Traffic Sign Benchmark actually has the signs divided into groups: speed…

• 3 min read
neural networks , CNN , hierarchical neural networks

Verification

Fine Tuning of Coverage Model Definition

Functional Coverage is one of the main means to measure the quality and progress…

• 8 min read
funtional verification , Specman , coverage , Functional Verification , Coverage-Driven Verification , CDV , e , e language , Funcional Verification , team specman , Verification IP modeling , metric-driven verification , MDV

Academic Network

Cadence Academic Network in Poland

Poland is a country with long tradition in microelectronics education and research…

• 2 min read
university , Cadence Academic Network , Poland , university program

Academic Network

PRIME and SMACD Conferences in Lisbon

Cadence Academic Network is supporting for years PRIME (PhD Research in Microelectronics…

• 2 min read
Cadence Academic Network , academic workshop , ADE , Virtuoso

Breakfast Bytes

How to Optimize Your CNN

Convolutional neural nets (CNNs) are not programmed in the traditional sense, but…

• 4 min read
Low Power , cnn training , cnn optimization , neural networks , CNN , embedded neural nets

Academic Network

Students from Pohang University of Science and Technology Visit Cadence Headquar…

My team recently had the privilege of hosting first year undergraduate students aka…

• 1 min read
Cadence Academic Network

Academic Network

DAC: A Glimpse of the Future Innovators

Hope you read my previous blog on Cadence Academic Network sponsoring all the student…

• 1 min read
DAC , Cadence Academic Network

Whiteboard Wednesdays

Whiteboard Wednesdays - Gauging Signal Quality Using Eye Diagrams

In this week's Whiteboard Wednesdays video, Chung Huang summarizes his presentation…

• less than a min read
Whiteboard Wednesdays , eye diagrams , signal quality

Breakfast Bytes

Power-Efficient Recognition Systems for Embedded Applications

Neural networks are hot. Las Vegas is hot, too. And there is a connection. In late…

• 4 min read
Chris Rowen , training , neural networks , CNN , embedded

Breakfast Bytes

Last Chance to See Tsukiji Fish Market

This doesn’t have much to do with Cadence or semiconductors. It has a lot to do with…

• 5 min read
tsukiji , renasas , japan , tsukiji fish market

SoC and IP

How to Create a Working IoT Sensor in One Month

Cadence and ARM have created an IoT IP reference sub-system that can speed system…

• less than a min read
sensor , IoT , ARM , IoT subsystem , IoT sensor

Whiteboard Wednesdays

Whiteboard Wednesdays—Optimizing Neural Networks

In this week's Whiteboard Wednesdays video, Chris Rowen discusses optimizing neural…

• less than a min read
Whiteboard Wednesdays , IP , Chris Rowen , high throughput , low energy , Tensilica , neural networks

System, PCB, & Package Design 

Cadence Sigrity SystemSI Technology Highlighted at CDNLive SV 2016

This year’s CDNLive Silicon Valley developer conference had more than 125 presentations…

• 1 min read
PCB SI , PCB , SI , PCB Signal and power integrity , Signal Integrity , PCB design , Sigrity

Breakfast Bytes

Pieter Vorenkamp and IP at Cadence

Pieter Vorenkamp is the new(ish) senior VP and general manager of the semiconductor…

• 2 min read
IP , Pieter Vorenkamp , Breakfast Bytes

Breakfast Bytes

An Steegen's Secrets of Semiconductor Scaling

If you were asked where in the world the most leading-edge semiconductor research…

• 3 min read
scaling , an steegen , imec , FinFET , ITC , power , Breakfast Bytes , silicon nanowire
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