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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Verification

Product Update: New Assertion-Based Verification IP (ABVIP) Available Now

Verifiers rejoice: R&D has just released all-new Assertion-Based Verification IP…

• 2 min read
Incisive Formal Verifier , Jose Barandiaran , ABV , Functional Verification , ABVIP , formal , formal apps , assertions , IEV , Incisive Enterprise Simulator (IES) , Formal verification , IFV , verification , Assertion-based verification , IES-XL

Digital Design

10 Encounter Tips and Tricks You May Not Be Aware Of

In looking over the shoulders of Encounter users over the years I've found there…

• 1 min read
EDI , Routing , power routing , encounter digital implementation system , IC layout , NanoRoute , Tips , encounter , tips and tricks , Digital Implementation , signal routes , log file , tricks , tcl

Verification

Video: DVCon 2012 Digital-Mixed Signal (DMS) Expert Neyaz Khan on UVM Mixed Signal…

E-mail reminders for the DVCon 2013 Call For Abstracts prompted me to look through…

• 1 min read
digital mixed-signal , AMS , uvm , Joe Hupcey III , verification strategy , Verification methodology , Functional Verification , UVM-MS , Neyaz Khan , Mixed Signal Verification , Mixed-Signal , DVcon , Maxim Semiconductor , verification

Verification

My Constraint was Ignored – Is it a Tool Bug? – Part 2

In a previous post we showed some cases of user code that can cause ignored constraints…

• 3 min read
AF , IntelliGen , Specman , debug , Functional Verification , Generation , e language

Digital Design

Capturing and Processing Encounter Console Output with "redirect"

In my last post I wrote about writing more compact db access scripts with dbGet's…

• 4 min read
dbGet , EDI , write nets to file , Console output , encounter , redirect , Encounter Digital Implementation , Dwyer , tcl

System, PCB, & Package Design 

What's Good About Customer Support AppNotes? They Will Increase Your Productivity

Our Silicon Package Board (SPB) Customer Support team has initiated a new blog series…

• less than a min read
PCB , PCB Layout and routing , customer support , applications , Allegro 16.5 , Appnotes , PCB Editor , Allegro performance , Layout , design , PCB design , 16.5 , SPB16.5 , Allegro PCB Editor , application note , OrCAD PCB Editor , Online Support , Allegro

System, PCB, & Package Design 

Customer Support Recommended - Appnote on Increasing Performance in Allegro PCB …

While working on very large scale Printed Circuit Board (PCB) files that contain…

• 1 min read
COS , PCB , PCB Layout and routing , customer support , Performance Advisor , Support , Allegro 16.5 , PCB Editor , Allegro performance , Layout , Appnote , dbdoctor , PCB design , SPB16.5 , Allegro PCB Editor , application note , Online Support , Allegro

Verification

UVM Testflow Phase Debugging- Identifying Blocking Activities

UVM Testflow debugging capabilities have been recently enhanced through the addition…

• 1 min read
AF , uvm , Specman , methodology , Testflow , Functional Verification , testflow phase debugging , testflow phases , advanced verification , e language , blocking activities , IES-XL

Analog/Custom Design

Mixed-Signal Gets Clear Message in China

While most of my colleagues in the US were taking a nice break during the July 4…

• 3 min read
mixed-signal seminars , Beijing , AMS , China , mixed signal design , Technology on tour , mixed-signal ToT , mixed-signal methodology , mixed signal methodology , tech on tour , mixed signal solution , analog , Mixed-Signal , Shenzhen , mixed signal methodology guide , mixed signal , ARM , tech-on-tour , Shanghai , AMS Verification , mixed-signal verification

Digital Design

Improve Your Productivity With Rapid Adoption Kits (RAKs) for Encounter Digital Implementation…

As you know, Cadence Online Support is your 24/7 site for getting help and resolving…

• 2 min read
SoC-Encounter , Cadence On-Line Support , Low Power , Foundation Flow , DBTcl , EDI system , Signoff Analysis , Low-Power , EDI 11.1 , Cadence Online Support , NanoRoute , Silicon Realization , Digital Implementation , EDI system Encounter Digital Implementation System , CTS , Enouter Timing System , Rapid Adoption Kits , RAKs , SoC-Encounter dbGet dbSet

Verification

Using Flexible Specman License Searches

Until recently, Specman used to look for its licenses in the following strict, hardcoded…

• 2 min read
AF , Specman , new features , Functional Verification , licenses , license search , Incisive , e language , Specman licenses , verification , IES-XL

Verification

Adding Xilinx C Models to the Virtual Platform of the Zynq-7000 EPP

Today, I have a good article from Henry Von Bank of Posedge Software related to Zynq…

• 5 min read
Virtual System Platform , zynq , virtual platforms , TLM , posedge , IP-XACT , Henry Von Bank , virtual prototypes , VSP , RDF , SystemC , xilinx , ARM , FFT , Zynq virtual platform , Zynq-7000

System, PCB, & Package Design 

What's Good About Capture’s CIS INI Settings? Look to SPB16.5 and See!

This week, I'm providing a very short blog. While the content is brief and simple…

• less than a min read
capture , "capture CIS" , OrCAD Capture Marketplace , OrCAD Capture , Capture CIS , Capture-CIS , Allegro 16.5 , SPB , design , OrCAD , Design Entry , SPB16.5 , PCB Capture , Schematic

Verification

DAC 2012 Video: Dr. Kerstin Eder, University of Bristol, About Her Course on Functional…

Dr. Kerstin Eder, a Senior Lecturer in the Computer Science department at the University…

• 1 min read
DAC , uvm , Joe Hupcey III , interview , Functional Verification , video , Dr. Kerstin Eder , University of Bristol , DAC 2012

Verification

C-to-Silicon Japan User Group and Ikegami Production Experience

We have been seeing some rapid growth in adoption of C-to-Silicon Compiler high-level…

• 2 min read
High-Level Synthesis , customers , Maesato , japan , Japan user group , Ikegami , SystemC , C-to-Silicon Compiler , Synthesis , Virtex-6 , HLS , ESL , FPGA

Verification

DAC2012: Xilinx Zynq-7000 - From RTL to Success with Emulation

It is nice to see when visions get closer to reality. When Cadence announced its…

• 4 min read
DAC , Virtual System Platform , zynq , cadence , Acceleration , debug , Functional Verification , System Design and Verification , System Development Suite , embedded software , Emulation , virtual prototype , Software Development and Debug , firmware , Performance Analysis , xilinx , DAC 2012 , Design Automation Conference , system integration

Verification

Video: DAC 2012 Update on AMIQ’s DVT IDE – New RTL Design Work Flow Support

Readers of this blog and of Team Specman will recall that Integrated Development…

• less than a min read
DAC , eclipse , Joe Hupcey III , Cristian Amitroaie , DVT , AMIQ , DAC 2012 , RTL design , integrated development environment , IDE

Verification

SystemC TLM-2.0 Virtual Platform Direct Memory Interface (DMI) Performance Impac…

One of the most interesting concepts in SystemC TLM-2.0 is the concept of Direct…

• 4 min read
Direct Memory Interface , Zynq-7000' , SystemC , Virtual Platforms , linux

Verification

DAC 2012: The Top Seven Reasons for using FPGA Based Prototyping

John Blyler, Editorial Director at Extension Media , presented in our EDA360 Theatre…

• 3 min read
RPP , FPGA Based Prototyping , Custom FPGA Boards , hardware/software integration , cadence , Acceleration , debug , Functional Verification , System Design and Verification , System Development Suite , embedded software , JTAG , Emulation , virtual prototype , Software Development and Debug , xilinx , DAC 2012 , HAPS , John Blyler , Design Automation Conference , system integration , FPGA
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