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Corporate News

Accelerating System Design with Real-Time Simulation, Powered by AI Physics

Rising demand for AI infrastructure is driving faster innovation and smarter use…

Corporate
• 4 min read
CFD , featured , NVIDIA , accelerated compute , millennium

Analog/Custom Design

Virtuoso Studio IC25.1 ISR2 Now Available

Virtuoso Studio IC25.1 ISR2 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Data Center

Innovation in Data Center Design and Operations: Highlights from Thésée Event

The Thésée event brought together key partners like France Télévisions, Thésée, Cadence…

Veena Parthan
• 5 min read
featured , Thésée Event , data center , Cadence Reality Digital Twin Platform

Corporate News

Don’t Miss the 2025 North America Open Meeting!

Join Visionaries, Discover Breakthrough Tech, and Power Your Next Big Idea Are you…

Corporate
• 1 min read
featured , innovation , Beta CAE , event , AI
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Blog - Post List

Latest blogs

SoC and IP

Low Latency DRAMs Continue to Serve Networking Niches

Low Latency DRAMs (LL DRAMs), Survive to Serve an Important Market Niche: Last…

• 4 min read

System, PCB, & Package Design 

Allegro PCB SI at DesignCon

Drop by the Cadence booth at DesignCon to see the latest demonstrations of Allegro…

• less than a min read
PCB Signal and power integrity , IBIS-AMI , SerDes , PCB design , DDR3

System, PCB, & Package Design 

Cadence SiP and IC Packaging at DesignCon

Those of you attending DesignCon in February should stop by the Cadence booth to…

• less than a min read
Digital SiP design , 3D-IC , TSV , IC Packaging & SiP design , IC Package Physical layout and co-design

RF Engineering

SpectreRF GUI Support for MMSIM 7.1

MMSIM 7.1 has just been released! The following IC release GUIs support the new MMSIM7…

• less than a min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design

Digital Design

ST Microelectronics – A Fountain-head of Design Innovations

In my last blog, I asked all of you to send me your design innovations. Thanks for…

• 1 min read
SoC-Encounter , SoC-Encounter 8.1 , Digital Implementation , Encounter Digital Implementation , "SoC-Encounter"

Verification

Functional Verification More Important than Ever in 2009?

Here in Cadence Product Marketing, we're still recovering from our very busy annual…

• 1 min read
metric driven verification (MDV) , Functional Verification , Formal Analysis , Coverage-Driven Verification , coverage driven verification (CDV) , OVM 2.0

System, PCB, & Package Design 

3D IC or TSV: The Next Phase in Functional Density and Miniaturization

It seems that almost every semiconductor company is thinking or talking about 3D…

• less than a min read
Analog and RF SiP design , Digital SiP design , TSVi , IC Packaging & SiP design , IC Package Physical layout and co-design

Verification

Report On The MDV "Deep Dive" Workshops

As heralded in a prior posts, we recently hosted some "alumni" from our recent Techtorials…

• 6 min read
workshops , verification strategy , Verification methodology , metric driven verification (MDV) , Coverage-Driven Verification , Multi-domain verification: HW/SW co-verification , Enterprise Manager , Enterprise Planner , ISX (Incisive Software Extensions) , Plan and metrics management , coverage driven verification (CDV) , ISX , Incisive Enterprise Simulator (IES) , techtorial

SoC and IP

DRAM Market Problems Escape All Solutions So Far

DRAM Market Solution? You Won’t Find It Here!: If you are reading here, expecting…

• 5 min read

System, PCB, & Package Design 

What's Good About Updated Assembly Design Rules Checker? - Look to SPB16.2 and See

As packages continue to increase in complexity, particularly in the arrangement of…

• 5 min read
SPB 16.2 , Design Rule Checker , PCB design , Allegro

Verification

Exploring the Virtual Platform Part 2

This week's installment of the "Exploring the Virtual Platform" series focuses on…

• 5 min read
virtual platform , System Design and Verification , ARM , linux , QEMU

SoC and IP

SLC Price Premium and Profit Potential Persists

SLC NAND is More Profitable than MLC, Though Market is Quite Limited : Digitimes…

• 3 min read

Verification

Tech Tip: Managing Specman esv File Size

When compiling e files on top of Specman, or when using the save command, Specman…

• less than a min read
Specman , e , Incisive Enterprise Simulator (IES) , IES

Verification

Ride The Economy Slow-Down

Last week, at Cadence Sales Kickoff, we have heard fascinating presentations from…

• less than a min read
System Design and Verification , IP re-use , ASIC/ASSP

Verification

New AEware: Generate vr_ad Definitions for IP-XACT XML IP Blocks

[Please welcome guest blogger Steve Hobbs, an Application Engineer in our Field…

• 5 min read
Specman , IP-XACT , vr_ad , Register Package , e , Spirit

Verification

VIP Following OVM Frees Users to Choose SystemVerilog and e

Back in November Cadence introduced a vastly expanded verification IP portfolio using…

• 1 min read
SystemVerilog , OVM , VIP , e , multi-language , eRM

Verification

Welcome to the "Exploring the Virtual Platform" Series

Today I'm starting a series of articles related to what is commonly called the Virtual…

• 5 min read
virtual platform , System Design and Verification , virtual protoype

Verification

Aart DeGeus' Surprise Comment at Last Night's EDAC CEO Forum

Last night the Electronic Design Automation Consortium ("EDAC", the trade group for…

• 2 min read
IEEE 1647 , events , Functional Verification , e , EDAC

Verification

Generation Debugging With "IntelliGen" (With Video)

You might have seen the Generation Debugger of Specman's new Generation Engine IntelliGen…

• 3 min read
IntelliGen , Specman , e , Incisive Enterprise Simulator (IES) , IES
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