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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Verification

LPDDR6: The Next-Generation LPDDR Device Standard and How It Differs from LPDDR5

Low-power DDR SDRAM has been one of the most widely used memories in the semiconductor…

• 4 min read
Verification IP , LOW POWER DRAM , JEDEC , LPDDR6 Vs LPDDR5 , DRAM , lpddr5 , lpddr5x , memory models , Lpddr6

Verification

UEC-LLR: The Future of Loss Recovery in Ethernet for AI and HPC

As Artificial Intelligence (AI) and High-Performance Computing (HPC) systems become…

• 2 min read
Verification IP , artificial intelligence , uvm , LLR , Functional Verification , UEC , Ethernet , HPC , Ethernet UEC , AI/ML

Digital Design

Silicon Signoff and Verification 25.1 Base Release Now Available

The Silicon Signoff and Verification (SSV) 25.1 release is now available for download

• 7 min read
ECO , inter-power domain , Silicon Signoff and Verification , power-up analysis , Voltus IC Power Integrity Solution , Tempus , cell electromigration , 3D-IC , Voltus InsightAI , advanced multi-input switching , Power Analysis , 3D-IC Technology , certus , skew , Skew Modeling and Analysis , vectorless

Verification

MIPI MPHY 6.0: Enabling Next-Generation UFS Performance

High-speed chip-to-chip data transfer is continuously evolving to meet increasing…

• 1 min read
Verification IP , UniPro , MIPI Alliance , VIP , MIPI , MPHY

Corporate News

Baylor University and Olssen Optimize Data Centers with Cadence

Data center infrastructure is changing in tandem with the advancements in AI and…

• 2 min read
designed with cadence

System, PCB, & Package Design 

Discover Hidden Gems: Must-See Underrated Cadence Community PCB Design Threads

Explore hidden gems in Cadence Community Forums—underrated PCB design threads packed…

• 2 min read
PCB , community forum , PCB design , allegro x , SKILL , tcl

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso , Custom IC Design , Custom IC , IC design , IC23.1

Verification

Celebrating LPDDR6 Specification Publication: Cadence Hosts JEDEC LPDDR Meeting

Low-power DDR SDRAM is one of the most widely used memories in the semiconductor…

• 2 min read
Verification IP , Design IP , JEDEC , LPDDR PHY IP , DRAM , lpddr5 , LPDDR Controller IP , memory models , Lpddr6

Digital Design

Budgeting Power Like A Pro: Don't Let Your Chip Max Out Its Power Credit Limit

Power planning in chip design is a lot like managing your monthly budget. If you…

• 6 min read
Genus , low-power technique , training , Optimize , online training

SoC and IP

Designing the AI Factories: Unlocking Innovation with Intelligent IP

The rapid evolution of artificial intelligence (AI) is reshaping the technological…

• 3 min read
IP , AI Factories , memory IP , semiconductor IP , Memory Modules , AI

Computational Fluid Dynamics

Professionals in CFD with Dr. Amalia Argyridi

In this edition of the Professionals in CFD series, we are happy to feature Dr. Amalia…

• 5 min read
Beta CAE , Computational Fluid Dynamics , WomenAtCadence , women in engineering , Women in CFD

Analog/Custom Design

Virtuoso Studio IC25.1: Explore the New Features - One Byte at a Time

This blog highlights six exciting new features in Virtuoso Studio IC25.1, showcasing…

• 6 min read
Place like Layout in Photonics , Turbo Bus Toolbar , ignore parameter check , Cadence blogs , Virtuoso Dashboard , color binding in layout , Multi-layer Bus Routing , smart search in SKILL API Finder , Turbo Bus , Virtuoso , Custom IC Design , Virtuoso Layout Suite , SKILL

Digital Design

Innovus Implementation System 25.1: A Big Leap Forward

The latest Innovus 25.1 major release, packed full of new features and improvements…

• 2 min read
Stylus Common UI , Innovus Implementation System , RTL synthesis

SoC and IP

LPDDR6: A New Standard and Memory Choice for AI Data Center Applications

LPDDR SDRAM, initially developed for low-power mobile devices such as smartphones…

• 2 min read
ddr5 , LPDDR , hbm4 , LPDDR Controller IP , lpddr5x , AI training , Lpddr6

RF Engineering

Silicon MMIC Design with Cadence Virtuoso Studio RF Platform

Monolithic microwave integrated circuits (MMICs) combine passive and active components…

• 7 min read
microwave , RF , RF CMOS , mmwave , SiGe , ADS , MMIC , silicon

Corporate News

Understanding Agentic AI and Its Future in Autonomous Design

The semiconductor industry is at a pivotal crossroads, grappling with mounting challenges…

• 7 min read
reasoning models , featured , agentic ai , AI-Driven Design , ai-driven , optimization , AI/ML , autonomous design , interoperability protocols

Analog/Custom Design

How IC25.1 Enhances Functional Safety Analysis for Analog Fault Simulation

In the high-stakes world of automotive electronics, milliseconds matter. Imagine…

• 6 min read
IC25.1 , Analog Design Environment , functional safety , Midas Safety Platform , Cadence blogs , Virtuoso Studio , custom/analog , Virtuoso New Design Platform , cadence , Analog Simulation , MMSIM , midas , IC Release Announcement blog , analog , ADE , training , Virtuoso Analog Design Environment , Cadence training , training bytes , Virtuoso , Spectre , Analog Design Environment , ADE Artist , Virtuosity , autostop , cadenceblogs , Virtuoso Video Diary , fault , Circuit Design , Cadence Education Services , IC Release Blog , analog design , Custom IC Design , fusa , Custom IC , Legato Reliability , custom design technology , ADE Assembler

System, PCB, & Package Design 

EMX Planar 3D Solver – New Key Features and Updates

The increasing complexity of chip designs that leverage 3D-IC technology , heterogeneous…

• 3 min read
fill approximation , 3D-IC , white boxing , black boxing , Virtuoso , crosstalk , Meshing , EM Solvers , EMX Solver

System, PCB, & Package Design 

BoardSurfers: Training Insights: Stay Up-to-Date on the PCB Editor Enhancements

In the ever-evolving world of technology, it is crucial for professionals to stay…

• 3 min read
PCB Layout and routing , Allegro X PCB Editor , BoardSurfers , PCB Editor , PCB design , Training Insights , Constraints , allegro x
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