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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
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Blog - Post List
Latest blogs

Breakfast Bytes

AEK: Semiconductors: The Base for the Software-Defined Car

At this year's Automobil Elektronik Kongress, there was a panel session titled Semiconductors…

• 10 min read
risc-v , NXP , mercedes-benz , ARM , automobil elektronik kongress

Computational Fluid Dynamics

Seakeeping Observations of SA Agulhas II Using Cadence Fidelity FINE/Marine

The shift left approach is slowly being realized and employed in the marine industry…

• 3 min read
CFD , Marine Engineering , C-Wizard , Pointwise , Fidelity CFD , engineering , simulation software , NUMECA , Meshing , Ships , seakeeping

Breakfast Bytes

Automobil Elektronik Kongress 2022

For me, the must-attend event to understand what is going on in the automobile industry…

• 5 min read
Automotive , automobile elektronik kongress , aek , ludwigsburg

Verification

Stay Ahead of Competition with Real-Time Cross-Team Collaborations

To stay ahead in competition in chip design real-time collaborations ensure traceability…

• 4 min read
collaboration , Palladium , verification management , Traceability , vManager

Life at Cadence

What’s Driving the Automotive Industry in 2022?

Cars are becoming computers on wheels with more processing power than the average…

• 6 min read
Automotive

Breakfast Bytes

Cadence Expands into Molecular Simulation with Acquisition of OpenEye Scientific

This morning, Cadence announced that it has entered into a definitive agreement to…

• 3 min read
openeye scientific , openeye , orion , molecular simulation

Analog/Custom Design

Spectre Tech Tips: Introducing Spectre X EMIR Voltus-XFi

This blog describes the new capabilities in Spectre 21.1 ISR2 through which it provides…

• 3 min read
Spectre X EMIR , Voltus-Fi-XL , Virtuoso Analog Design Environment , Spectre X distributed simulation , Spectre X Simulator

Breakfast Bytes

CadenceLIVE: Pegasus on AWS, Let Physical Verification Fly

At CadenceLIVE Silicon Valley, Ahmed Elzeftawi of AWS and Dibyendu Goswami of Cadence…

• 4 min read
Physical verification , pegasus , DRC , cloud , aws , cadence cloud

Academic Network

Cadence Academic Network at 59DAC

The Cadence Academic Network was excited to participate in many activities at the…

• 2 min read
DAC , Young Fellows , featured , Cadence Academic Network , CMC Microsystems

System, PCB, & Package Design 

In-Design Analysis in the Cloud with Cadence OnCloud

Last month at CadenceLive Silicon Valley, Cadence introduced a software-as-a-service…

• less than a min read
Power Integrity , in-design analysis , Signal Integrity , electromagnetic , thermal

Breakfast Bytes

ITF USA: Luc Van den hove on Deep Tech

The afternoon of the Monday of SEMICON West is always the Imec Technology Forum …

• 6 min read
itf usa 2022 , imec , itf

System, PCB, & Package Design 

System Analysis Knowledge Bytes: Accelerating Early Stage Design Sign-Off Using PCIe…

This blog talks about how the Cadence®︎ AdvancedSI tools, which are packaged in the…

• 4 min read
Sigrity and Systems Analysis , High Speed Structure Optimization , PCIe , Signal Integrity , High Speed design , power-aware SI

Breakfast Bytes

CadenceLIVE: Do You Know What CMP Is?

I was talking to someone at Cadence recently and I was surprised that he didn't know…

• 4 min read
CMP

System, PCB, & Package Design 

Shift Left: Moving Multiphysics into the Mainstream

As electronic systems have grown incrementally more complex, with more features packed…

• 1 min read
in-design analysis , Electromagnetic analysis , Signal Integrity , Thermal Analysis , microwave design

Breakfast Bytes

Andreas Kuehlmann and Tortuga Logic...I Mean Cycuity

I was in San Francisco for the RSA security conference. On Monday, it has tutorials…

• 2 min read
tortuga logic , cycuity , common weakness enumeration

RF /マイクロ波設計

μWaveRiders:新しいPythonライブラリは、Cadence AWR Design Environmentで高レベルのAPIを提供します

新しいPythonライブラリは、Pythonのコーディング規則により厳密に準拠したコマンド構造を使用して、PythonとAWRソフトウェア間のインターフェイスを容易にするために作成されました…

• less than a min read
RF Simulation , Circuit simulation , AWR Design Environment , Graphing measurements , awr , Graphs , Tips/Tricks , Circuit Design , microwave office , japanese blog , measurements , Visual System Simulator(VSS)

RF Engineering

μWaveRiders: New Python Library Provides a Higher-Level API in the Cadence AWR Design…

A new Python library has been written to facilitate an interface between Python and…

• 5 min read
RF Simulation , Circuit simulation , AWR Design Environment , Python , API , pyawr utilities , awr , RF design , VBA , microwave office , Visual System Simulator (VSS) , scripting

Breakfast Bytes

June Update: CHIPS, Minis, and DI Water

My monthly update normally occurs on the last Friday of the month. But for June,…

• 4 min read
Intel , mini , di water , motorcycles , chips act

Verification

Xcelium PowerPlayBack App and Dynamic Power Analysis

Learn how Xcelium PowerPlayback App enables the massively parallel Xcelium replay…

• 5 min read
Dynamic Power Analysis , xcelium , power
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