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Featured

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
Corporate 25 Jun 2026 • 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
Corporate 24 Jun 2026 • 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
Corporate 23 Jun 2026 • 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA

Corporate News

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
Corporate 22 Jun 2026 • 8 min read
featured , physical ai , HGR , AI , Honda
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Blog - Post List
Latest blogs

Life at Cadence

IQM Is Building the Next Generation of Quantum Computers

IQM seeks to solve one of the greatest technological challenges globally: building…

Corporate 20 Oct 2022 • 1 min read
RF , awr , designed with cadence

Life at Cadence

RISC-V Is Thriving – Here’s What You Need to Know

RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley…

Corporate 20 Oct 2022 • 4 min read
risc-v

Breakfast Bytes

Latinx Heritage Month

Last week, Cadence held a Mercado Fiesta on the campus to celebrate Latinx Heritage…

Paul McLellan 20 Oct 2022 • 2 min read
latinx , latinx heritage month , Hispanic

Analog/Custom Design

Start Your Engines: Clone your AMS Designer Testcases and Rerun them Anywhere

Design Capture and Packaging (DCP) utility lets you isolate, capture and package…

Andre Baguenie 20 Oct 2022 • 5 min read
mixed signal design , AMS Designer , AMSD , Start Your Engines , Mixed-Signal , Design Capture , Cadence Community

Digital Design

HLS for AI/ML Models: TensorFlow to RTL

Artificial Intelligence (AI) plays a key role in semiconductors to meet the challenging…

Vinod Khera 19 Oct 2022 • 3 min read
Stratus HLS , Genus

Computational Fluid Dynamics

Augment Certainty of Bio-simulation Studies with Computational Fluid Dynamics

Computational fluid dynamic (CFD) simulations have a lot to offer for a top-level…

Veena Parthan 19 Oct 2022 • 4 min read
openeye scientific , molecular sciences , Computational Fluid Dynamics , fluid dynamics , Fidelity CFD , Cadence CFD , drug delivery mechanism

カスタムIC/ミックスシグナル

Spectre Tech Tips: ダイナミック電流密度チェック

デバイスと回路の信頼性は、個々のMOSFET デバイスが短時間に消費する電力と、発生する熱の量に大きく依存しています。信頼性と寿命を向上するために、回路設計者はデザイン内のデバイスの消費電力を最適化する必要があります…

Custom IC Japan 19 Oct 2022 • 1 min read
spectre aps , Spectre 21.1 , Dynamic Checks , Dynamic design checks , Spectre Circuit Simulator , Spectre , japanese blog , spectre x

Verification

USB4 Version 2.0 – Next frontier in High-Speed Data Tunneling

USB4 Version 2.0 specification was recently released by the USB Promoter Group. This…

Neelabh 19 Oct 2022 • 2 min read
USB4 VIP , USB4v2 , usb4 , USB4 Version 2

Computational Fluid Dynamics

Last Week at Fidelity CFD

It's Monday and time to look back on what happened last week here at Cadence Fidelity…

John Chawner 19 Oct 2022 • 3 min read
CFD , turbomachinery , webinars , Pointwise , Computational Fluid Dynamics , fluid dynamics , Fidelity CFD , Mesh Generation

Computational Fluid Dynamics

On-Demand Webinar - Predicting Aerodynamic Flow Around Automotive Vehicles

Predicting aerodynamic flow physics around automotive vehicles is a complex endeavor…

AnneMarie CFD 19 Oct 2022 • less than a min read
CFD , Automotive , external aerodynamics , automotive engineering , featured , Computational Fluid Dynamics , fluid dynamics , simulation software , Aerodynamics

Digital Design

Voltus Voice: How to Find Functional Power Vectors that Matter Quickly

Vector profiling enables ASIC designers to quickly identify areas with maximum activity…

bertrandgenneret 19 Oct 2022 • 6 min read
switching power , Low Power , Voltus IC Power Integrity Solution , power consumption , Power Signoff , Power Profile , Digital Implementation , switching activity , Power Analysis , vector profiling

Life at Cadence

Formula 1: Hybrid Design vs. Density and Compact Design Optimization

Understand the role that density and compact design optimization play when designing…

Corporate 19 Oct 2022 • 5 min read
F1 , optimization , density , formula 1

Breakfast Bytes

USB-C – The Least Standard Standard Ever

In a post in our verification blog , Neelabh Singh told us that USB4 Version 2.0…

Paul McLellan 19 Oct 2022 • 3 min read
usb 4.0 , USB , USB-C

Verification

Leveraging the PCIe for CXL Mode Link Up Using Alternate Protocol Negotiation Te…

An Alternate Protocol negotiation (APN) can be understood as a non-PCIe protocol…

Somya Bansal 19 Oct 2022 • 3 min read
CXL , Verification IP , cadence , Functional Verification , VIP , PCIe , coherency , TripleCheck

Breakfast Bytes

HOT CHIPS: Arm's Morello

HOT CHIPS was back in the summer, and I covered it in two overview posts (and some…

Paul McLellan 18 Oct 2022 • 5 min read
morello , hot chips , ARM , cheri , capability

System, PCB, & Package Design 

Enflame Unveils Lab-Correlated Design and Analysis Methodology for 2.5D HBM Desi…

At CadenceLIVE China 2022, AI-startup, Enflame Technology, revealed how their engineering…

Sigrity 17 Oct 2022 • less than a min read
SI , PI , IC , SSN anlysis , IC Packaging , Sigrity XcitePI , Co-Analysis , Power Integrity , CadenceLIVE China , Advanced-IC Package design , silicon interposer , Signal Integrity , 2.5D HBM , cadencelive , Sigrity SystemSI , Clarity 3D Solver , simulation

Verification

CXL 3.0 Scales the Future Data Center

CXL is emerging as the industry focal point for coherent I/O with Open CAPI and Gen…

Claire Ying 17 Oct 2022 • 4 min read
CXL , Verification IP , Memory , System Design and Verification , VIP , PCIe , Funcional Verification , coherency , PCIe 6.0 , AI , data centers , cloud computing , verification

Breakfast Bytes

CadenceLIVE Boston: State-of-the-Art Heterogeneous Integrated Packaging (SHIP)

Congress and the military love to come up with cute acronyms for programs, and so…

Paul McLellan 17 Oct 2022 • 3 min read
RF , SiP , ship , ship-rf , 3dhi

Verification

Unraveling New Introduced PCIe 6.0 L0p

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

xinmu 17 Oct 2022 • 4 min read
Verification IP , VIP , PCIe , pcie gen6 , verification
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