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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

Digital Design

DAC 2010 – A “Coming Out” Party For 3D-IC Design

Overall, the 2010 Anaheim DAC was livelier than the years before. Customer and vendor…

• 2 min read
DATE , CSV , 3DIC , TSV , Wirebond , Digital Implementation , 3D , stacked die , flip chip , PoP

SoC and IP

New Freescale ARM-M4 and ColdFire-based 32-bit microcontrollers feature on-chip nanocrystal…

June’s Microprocessor Report carries an article written by Editor-in-Chief Jim Turley…

• 3 min read

SoC and IP

Intel + Best Buy + SSD = Sign of the Times

Intel recently announced that Best Buy is now carrying its retail-boxed X25-M (mainstream…

• less than a min read

Verification

Tech Tip On Verification Environment Re-Use

Verification has come a long way this past year, the highlight of which is UVM. UVM…

• 1 min read
Verification methodology , metric driven verification (MDV) , Functional Verification , OVM , Plan and metrics management

Verification

DAC Perspective One Week Later

DAC in Anaheim last week was as busy as always, perhaps more so, and of course I…

• 2 min read
DAC , uvm , Functional Verification , OVM , EDA360 , Denali , MDV

Verification

IntelliGen Moving Into The Spotlight With Pgen Deprecation

Specman's new Aspect Oriented Generation Engine, IntelliGen, has now been in service…

• 1 min read
IntelliGen , Specman , VIP , EDA , e , Funcional Verification , team specman , specman elite , Aspect Oriented Programming , CMS , Incisive Enterprise Simulator (IES) , AOP , IES-XL

SoC and IP

Elpida, Powertech Technology, and UMC team up to mate SOCs and memory using 3D design…

The idea of 3D wafer stacking isn’t new. I wrote an article about 3D assembly of…

• 1 min read

SoC and IP

SanDisk’s WORM (write-once, read mostly) SD card can’t be altered once written. Good…

SanDisk has just unveiled a WORM (write-once, read mostly) variant of the ubiquitous…

• 1 min read

System, PCB, & Package Design 

What's Good About Vias And The Allegro Router? SPB16.3 Has A Few New Enhancements

A few new enhancements specific to vias in the SPB16.3 release of Allegro PCB Editor…

• 4 min read
PCB , PCB Layout and routing , SPB16.3 , Allegro 16.3 , SPB 16.3 , PCB Editor , Layout , via , "PCB design" , PCB design , Allegro PCB Editor , microvia , Allegro

SoC and IP

MemCon 2010 Agenda. July 28, Santa Clara, California. Register Now.

MemCon is coming up next month, on July 28 in Santa Clara, California. Here’s a list…

• 1 min read

Verification

DAC360: Photo blog of DAC 2010 in Anaheim, CA

Click here or on the image below to go to the annotated photo blog of DAC 2010. Images…

• less than a min read
DAC , Specman , TLM , Functional Verification , IBM , OVM , EDA360 , TSMC , Palladium XP , Mike Stellfox , Denali , iPad , AMIQ , Twitter , XJTAG , IEV , Incisive Enterprise Simulator (IES) , Accellera VIP TSC , IFV , IES-XL

SoC and IP

Xilinx unleashes triad of low-power, 28nm FPGA families with very promising characteristics…

Today, Xilinx unveiled three new series of FPGAs all based on 28nm process technology…

• 2 min read

SoC and IP

ProMOS in Taiwan brings up Elpida 63nm process, successfully builds 1-Gbit DDR3 …

Taiwan DRAM maker ProMOS has just announced successful fabrication of 1-Gbit DDR3…

• 1 min read

Verification

DAC Cabbie Taught Me All I Need to Know About Verification

Confidence from competence. Measurement through metrics. Sell without selling. These…

• 4 min read
SystemVerilog , DAC , uvm , ABV , OVM , EDA360 , Register Package , Incisive , Funcional Verification , AMIQ , Twitter , MDV , Accellera VIP TSC , IES , VMM

SoC and IP

Samsung’s 512 Gbyte SSD pushes SATA 3 Gbps to the limit with “30nm class” Toggle…

Samsung just announced that it will be in volume production with a high-speed, 512…

• less than a min read

Verification

What's The Best Way To Reduce SoC Development Costs?

Before I got started with my DAC 2010 customer meetings on Monday morning, I stopped…

• 2 min read
TLM2 , virtual platforms , virtual prototypes , SystemC , DAC 2010

Verification

Hit The Road - DAC!

OK, now that the Design Automation Conference (DAC) seems to be rotating among San…

• 1 min read
DAC , uvm , Functional Verification , OVM

Verification

Snapshots From Day 0 of DAC 2010

Below are some snapshots of some "day 0" events, and last minute DAC preparations…

• less than a min read
DAC , uvm , OVM , Palladium XP

Verification

Advanced Option Brings New Features to Specman/e Users

Great news for Specmaniacs -- a new Specman Advanced Option is being announced at…

• 1 min read
SystemVerilog , DAC , Specman , Functional Verification , Multi-Core , e , team specman , specman elite , Incisive Enterprise Simulator (IES) , IES-XL
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