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Featured

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか?」をテーマに、本田技術研究所社 先進技術研究所(HGRX)との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
Cadence Japan 8 Oct 2025 • less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
Sheryl G 7 Oct 2025 • 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
Corporate 2 Oct 2025 • 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
Corporate 1 Oct 2025 • 4 min read
Edge AI , featured , Ambarella
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Blog - Post List

Latest blogs

SoC and IP

An inconvenient truth about using DDR3 SDRAM for embedded designs

DDR (double data rate) memory chips mounted on DIMMs have long been the mainstay…

archive 4 Jun 2010 • 3 min read

Verification

EDA360 And The "Paperback Computer"

Have you ever heard an assertion that's so intriguing and farsighted that it sticks…

jvh3 3 Jun 2010 • 7 min read
events , DAC , IP , paperback computer , innovation , metric driven verification (MDV) , Functional Verification , Advanced Node , EDA360 , Verification IP modeling , EDAC

SoC and IP

Storage Analyst Jim Handy says “NAND Cache is Back!”

Storage analyst and Grand Poobah Jim Handy has just released a free White Paper titled…

archive 3 Jun 2010 • 2 min read

SoC and IP

Kingston shows HyperX USB 3.0 SSD prototype at Computex

Earlier, this blog reported on OCZ’s Enyo USB 3.0 SSD and now at a private event…

archive 3 Jun 2010 • 1 min read

Verification

Making an EDA360 System Realization Investment Through Standards Support

Cadence is a sponsor of the Open SystemC Initiative (OSCI) standards organization…

Steve Brown 3 Jun 2010 • less than a min read
TLM , C-to-Silcon , OSCI , ESL

SoC and IP

Introduced at Computex: OCZ’s speedy RevoDrive brings PCIe SSD to consumer-class…

PC add-on vendor OCZ plays in several high-performance PC component markets including…

archive 2 Jun 2010 • 1 min read

Verification

C-to-Silicon Compiler 10.1 - Ease Of Use And RTL QoR

In the continuing effort to make high-level synthesis more viable to mainstream RTL…

Steve Brown 2 Jun 2010 • 1 min read
CTOS , TLM , C-to-Silicon , Synthesis , HLS

SoC and IP

Hitachi’s Z HDDs: Will 2.5mm less height make a difference? For SSDs?

Hitachi just shaved 2.5mm off of the top of its 2.5-inch laptop hard drives, producing…

archive 1 Jun 2010 • 1 min read

SoC and IP

More details on and system-design implications of the Hitachi-LG Data Storage HyDrive…

As discussed last week in this blog, Hitachi-LG Data Storage (HLDS)--an OEM vendor…

archive 1 Jun 2010 • 3 min read

System, PCB, & Package Design 

What's Good About AMS Simulator And Cursors? You’ll Need The SPB16.3 Release To See

With the SPB16.3 release of AMS Simulator , several new cursor enhancements are available…

Jerry GenPart 1 Jun 2010 • 1 min read
AMS , AMS simulator , SPB 16.3 , PSPICE , SPB , AMS simulation , Schematic

SoC and IP

ST Microelectronics’ SPEAr1300 embedded MCU features 600MHz dual-core ARM Cortex…

A few days ago, this blog discussed the “big resistor” model of SDRAM power consumption…

archive 28 May 2010 • 2 min read

Verification

TLM 2.0 As Part Of The EDA360 Vision

Ann Steffora Mutschler recently covered in her blog the progress the industry has…

Ran Avinun 28 May 2010 • 1 min read
TLM , virtual platform , TLM 2.0 , EDA360 , virtual prototype , SystemC , Synthesis , System Design and Verification

System, PCB, & Package Design 

Catch A Full-Wave Summer Kickoff Webinar: CST 3D Extraction Integrated With Cadence…

Is there anyone who does not carry a mobile communication device anymore? Sending…

TeamAllegro 28 May 2010 • 1 min read
SPB16.3 , SiP , Analog and RF SiP design , Digital SiP design , Allegro 16.3 , APD , webinar , SI analysis and modeling

SoC and IP

How does a hybrid SSD/optical drive make sense?

Some combinations like chocolate with peanut butter, ice cream with peanuts and chocolate…

archive 28 May 2010 • 1 min read

Verification

EDA360 Is More Than Design IP Plus Software Drivers

I checked my Linked-In messages the other day and saw a survey by Girish Patil with…

tomacadence 27 May 2010 • 2 min read
IP , Functional Verification , Virtual Chips , Phoenix , inSilicon , VIP , EDA360 , Sand

SoC and IP

Does Samsung really scare Japan? EETimes’ Junko Yoshida thinks so.

EETimes' Junko Yoshida just published an article titled “5 reasons why Samsung scares…

archive 27 May 2010 • 1 min read

SoC and IP

Marc Greenberg’s “big resistor” model of semiconductor DRAM power consumption

Too many DRAM choices. If you want low power DRAM, do you choose LPDDR1, LPDDR2,…

archive 25 May 2010 • 2 min read

SoC and IP

OCZ Enyo USB 3.0 SSD reviewed by PC Perspective video

Earlier, we covered the announcement of OCZ’s Enyo USB 3.0 external SSD. Now PC Perspective…

archive 25 May 2010 • less than a min read

SoC and IP

InfoWeek video series chronicles storage and SSD Evolution. Part 1 runs 8 minutes…

Can you spare nine minutes to get a really good grounding in SSD concepts? No? How…

archive 25 May 2010 • 1 min read
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