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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Latest blogs

Breakfast Bytes

2022 Kaufman Award Honors Giovanni De Micheli

This year's Kaufman Award honors Giovanni De Micheli, usually known as Nanni. Of…

• 5 min read
Kaufman Award , CEDA , IEEE , kaufman hall of fame , esd alliance

Verification

Unraveling PCIe 6.0 FLIT Mode Challenges

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

• 6 min read
Verification IP , featured , verification strategy , Functional Verification , VIP , PCIe , pcie gen6 , verification

Analog/Custom Design

Virtuoso ICADVM20.1 ISR28 and IC6.1.8 ISR28 Now Available

The ICADVM20.1 ISR28 and IC6.1.8 ISR28 production releases are now available for…

• 2 min read
Analog Design Environment , Cadence blogs , ADE Explorer , cadence , Virtuoso RF Solution , IC Release Announcement blog , Virtuoso Visualization and Analysis XL , Layout EXL , ICADVM20.1 , IC Release Blog , Custom IC Design , Custom IC , IC6.1.8 , ADE Assembler , Virtuoso Layout Suite XL

Verification

Importance of MDIO Interface for Ethernet.

M edia I ndependent I nterface M anagement ( MIIM ), or M anagement D ata I nput…

• 1 min read
Verification IP , uvm , SoC verification , IP verification , Ethernet VIP , Functional Verification , Cadence VIP portfolio , MDIO Interface , Ethernet

Life at Cadence

How Is the Semiconductor Industry Handling Scaling: Is Moore's Law Still Alive?

The chip design industry is going through exciting times. Process nodes with smaller…

• 5 min read
advanced process nodes , Genus Synthesis Solution , Innovus Implementation

Digital Design

Relax in Summer with Cooler IC chips and Ice-Cream! Do you want to Explore the Recipe…

Are you passionate about cooking? Err... Don't think it is a regular cooking class…

• 1 min read
Low Power , Genus , IEEE 1801 , UPF , Synthesis

Breakfast Bytes

TSMC OIP Preview 2022

I have pointed out before that you really only get two opportunities a year to get…

• 2 min read
OIP , TSMC

Breakfast Bytes

Cadence Certus Closure Solution: Automated Full-Chip Optimization

Today, we announced the Cadence Certus Closure Solution, the first-of-its-kind fully…

• 2 min read
featured , Tempus , tempus eco , STA , static timing , certus

Life at Cadence

Artificial Intelligence Is Revolutionizing Computational Software

What does the term computational software mean? The shortest explanation is that…

• 4 min read
artificial intelligence , computational software , EDA , AI

Computational Fluid Dynamics

Last Week at Fidelity CFD

Rise and shine for another week in the world of CFD. Here's what you missed last…

• 3 min read
CFD , Marine Engineering , transition , FINE Marine , unsteady flow , turbomachinery , turbulence , tweak , Computational Fluid Dynamics , machine learning , webinar , nonlinear harmonic , cadencelive , Hydraulic Turbines , nlh , Mesh Generation

Breakfast Bytes

3D Heterogeneous Integration (3DHI)

Shakespeare (in Romeo and Juliet) wrote: What's in a name? That which we call a…

• 4 min read
system-in-package , SiP , featured , chiplet , 3dhi , system-on-chip , 3DIC , SoC , 2.5D IC , heterogeneous integration

Academic Network

Academic and Entrepreneur Tracks at CadenceLIVE Europe 2022

I am very happy to announce that registration for the in-person CadenceLIVE Europe…

• 2 min read

Verification

USB4 Version 2.0 Announced

USB Promoter Group has announced the pending release of the USB4® Version 2.0 specification…

• less than a min read
usb4

Computational Fluid Dynamics

Generate Quads/Hexes at the Speed of Trias

The quadrilateral-dominant meshing algorithm within Fidelity Pointwise generates…

• 4 min read
CFD , Meshing Monday , Pointwise , Fidelity CFD , engineering , simulation software , Cadence CFD , Meshing , meshing algorithms

Breakfast Bytes

Tesla AI Day 2022

On Friday, September 30th, from 6 pm until well after 9 pm Tesla held its AI Day…

• 6 min read
Automotive , tesla , optimus , SDC , robot , AI

Verification

Struggling with Coverage Convergence – Give your Verification Wings with Xcelium…

Functional verification consumes more than 70% of the labor invested in today’s SoC…

• 1 min read
coverage , machine learning , xcelium , simulation

PCB設計／ICパッケージ設計

APD Plus を日本語で自習してみませんか？

Cadence Response Center (CRC)のホームページには、”ラーニング”というメニューがあり、製品の操作法や活用法を学習していただくのに便利な情報へのリンクが集められています…

• less than a min read
APD+ , 17.4 , APD , RAK , SPB17.4 , Allegro Package Designer , 17.4-2019 , japanese blog , Allegro

Life at Cadence

NVIDIA Embraces the Groundbreaking Technology, Dynamic Duo 2.0

When it comes to accelerated computing, NVIDIA is an industry pioneer, particularly…

• 1 min read
designed with cadence , chips

Life at Cadence

Heterogeneous Integration Co-Design Won’t Be Easy – Here’s What You Need to Succ…

Heterogeneous integration is ushering in a new era of silicon chip design with collaboration…

• 4 min read
featured , 3D-IC , heterogeneous integration
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