Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Computational Fluid Dynamics

This Week in CFD

Despite this being the Halloween time of year, this week's roundup of CFD news isn…

• less than a min read
CFD , Pointwise , Computational Fluid Dynamics , Mesh Generation , Omnis

System, PCB, & Package Design 

IC Packagers: Module Support in IC Package Design

It is quite common to reuse memory stacks across designs. These memory stacks are…

• 2 min read
APD , IC Packaging & SiP design , IC Packagers , Allegro Package Designer , 17.4-2019

Verification

Why is Ethernet Time-sensitive Networking (TSN) Adaptation So Rapid in the Automotive…

At a particular point in time, the automotive industry continued to add more and…

• 1 min read
Automotive , Verification IP , SoC verification , IP verification , Ethernet VIP , Functional Verification , VIP , Ethernet standards , Automotive Ethernet , TSN

Breakfast Bytes

Always Listening, HiFi 1 DSP

Today, at the Linley Processor Conference, we announced the latest addition to the…

• 4 min read
always on , audio , hifi 1 , Tensilica , hifi 1 dsp , earbuds

Life at Cadence

My Life at Cadence: Guillaume Foix

Cadence was recently ranked #7 on Newsweek’s Most Loved Workplaces list for 2021…

• 1 min read
Insights on Culture , Culture , cadence , GPTW , my life at cadence , life at cadence , cadence emea

Breakfast Bytes

October Update: GPTW, Intel Fabs, Apple, and More

These monthly updates normally occur on the last Friday of the month, but that is…

• 5 min read
Intel , Apple , semi , Arteris , apple m1

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: EMX Planar 3D Solverでのメッシュの表示

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
Virtuoso 3D Viewer , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Layers Assistant , EMX Models , Electromagnetic analysis , Virtuoso , EMX , japanese blog , Custom IC Design , EMX Solver , Virtuoso Layout Suite , Custom IC , 3D Mesh

System, PCB, & Package Design 

BoardSurfers: Training Insights: Manually Placing Components in Allegro PCB Edit…

Component placement is one of the most critical aspects of PCB designing. As the…

• 4 min read
BoardSurfers , 17.4-2019 , PCB design , Training Insights , Allegro PCB Editor , Allegro

定制IC芯片设计

Virtuoso Meets Maxwell：通过库实现系统分析和物理实现

欢迎阅读这篇博文了解如何创建组件和padstack库，以用于以Virtuoso 平台为驱动的多工艺流程。本文所描述的工具类似图书管理员的工作，它们必须通过各种途径来组装组件IP…

• 1 min read
Technology Independent Layout Pcell , Unified Library , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF Solution , Virtuoso RF , Virtuoso MultiTech , Electromagnetic analysis , librarian , SiP Layout Option , ICADVM20.1 , Cadence SiP Layout , TILP , Chinese blogs , VMM

Breakfast Bytes

TSMC OIP: 3DFabric and Integrity 3D-IC

Today is TSMC's OIP (or, to give it its full name, TSMC 2021 Online OIP Ecosystem…

• 3 min read
OIP , Integrity , TSMC , Innovus , integrity 3d-ic , 3dfabric

CFD（数値流体力学)

計算機航空宇宙とCFDの進化

初めに翼がありました。具体的には、1968年に超臨界の翼および翼を設計するために何か新しいものが必要であることが明らかになりました。今日では、シミュレーションによる航空機認証や…

• 1 min read
CFD , Aerospace , FLO22 , Pointwise , Computational Fluid Dynamics , CFD Applications , NUMECA , japanese blog , Mesh Generation

CFD（数値流体力学)

クワッドコプタードローンの飛行時間と航続距離の延長にOMNIS を活用

ドローンは、軍事、産業、個人消費者の領域において、幅広い用途での効率的なソリューションであることが証明されています。過去10年間でドローンの利用は急増しており、その年間成長率は50…

• less than a min read
CFD , Computational Fluid Dynamics , NUMECA , japanese blog

RF /マイクロ波設計

μWaveRiders:Cadence AWR Design Environment/プロジェクトブラウザのヒントとコツ

Team RF "μWaveRiders" ブログシリーズはCadence AWR RF製品のためのショーケースです。月ごとの話題はCadence AWR Design…

• 1 min read
microwave , RF Simulation , Circuit simulation , AWR Design Environment , awr , Tips/Tricks , RF design , japanese blog , Visual System Simulator(VSS)

Analog/Custom Design

Virtuoso ICADVM20.1 ISR21 and IC6.1.8 ISR21 Now Available

The ICADVM20.1 ISR21 and IC6.1.8 ISR21 production releases are now available for…

• 3 min read
Cadence blogs , ADE Explorer , IC Release , Announcement blog , Virtuoso RF Solution , Virtuoso , ICADVM20.1 , IC Release Blog , Custom IC Design , Custom IC , IC design , IC6.1.8 , Analog IC Design , ADE Assembler

RF Engineering

μWaveRiders: Cadence AWR Design Environment/Project Browser Tips & Tricks

AWR Software Tips & Tricks: Design Environment and Project Browser The first in the…

• 7 min read
RF Simulation , Circuit simulation , AWR Design Environment , awr , Tips/Tricks , RF design , microwave office , Visual System Simulator (VSS)

Life at Cadence

Celebrating a People-First Culture

I am very proud that Cadence has been recognized as #17 on Fortune’s World’s Best…

• 2 min read

Analog/Custom Design

Virtuoso Video Diary: Knowledge Booster Training Bytes Part 11 - Navigating Through…

This blog shows how you can easily navigate through tabbed Training byte channels…

• 4 min read
blended , channel , Spectre AMS Connector , Spectre AMS Designer , training , Mixed-Signal , digital badges , training bytes , Spectre , Cadence certified , Virtuoso ADE Explorer

Breakfast Bytes

Semiconductor 101...and Sunday Brunch

If you have been reading Breakfast Bytes regularly for the last couple of years,…

• 5 min read
sunday brunch , semiconductor 101

Digital Design

Voltus Voice: 6 Tips to Jump-start Your Voltus Stylus Migration Journey

Cadence Stylus UI streamlines the RTL-to-Signoff design flow, bringing all the Cadence…

• 5 min read
Voltus IC Power Integrity Solution , Tempus , Signoff Analysis , Digital Implementation , Innovus , stylus
CDNS - Fix Layout Hompage