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Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
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Blog - Post List
Latest blogs

PCB、IC封装：设计与仿真分析

什么是计算流体力学 (CFD)的 网格划分技术？

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章“ Please Excuse the Mesh:…

• less than a min read
网格划分 , CFD , Chinese blog , 计算流体力学 , Pointwise , 中文 , 系统分析 , 网格 , 多物理场仿真

Computational Fluid Dynamics

This Week in CFD

On this first Friday of October, we're happy to present This Week in CFD to help…

• less than a min read
CFD , Pointwise

Breakfast Bytes

AWS: Amazon's Own Experience with EDA in the Cloud

At CadenceLIVE Americas there was a cloud track. Opening the day was David Pellerin…

• 3 min read
aws , cadence cloud , Amazon

Analog/Custom Design

Spectre Tech Tips: Big Data with Spectre SQL Database

As a design gets bigger, simulation generates big data. As data gets bigger, so does…

• 3 min read
APS , Dynamic Checks , assert , Spectre , check , static checks

System, PCB, & Package Design 

IC Packagers: Off-the-Shelf Component Support for IC Package Designs

In Allegro® Package Designer Plus prior to the HotFix 019 of release 17.4-2019, any…

• 2 min read
die stack layers , APD , IC Packaging & SiP design , IC Packagers , Allegro Package Designer , 17.4-2019

Computational Fluid Dynamics

Cadence CFD on Social Media - What's New, What's Changed - UPDATED

Social media represents just one facet of how we at Cadence CFD communicate with…

• 1 min read
Pointwise , NUMECA

Breakfast Bytes

Floating Point Numbers: Why 0.1 + 0.2 Is Not 0.3

Floating-point numbers are widely used for numerical calculations, including digital…

• 4 min read

Computational Fluid Dynamics

Cadence at the NAFEMS World Congress

Cadence is thrilled to be a Gold Sponsor of the NAFEMS World Congress 2021 (25-29…

• 2 min read
CFD , Automotive , celsius , Pointwise , Computational Fluid Dynamics , simulation software , adaptation , Mesh Generation , NAFEMS , Omnis , clarity

Breakfast Bytes

A New Member of the Cadence 112G SerDes IP Family

Hyperscale data centers are bandwidth-hungry (and power-averse) and so the most important…

• 2 min read
112G-LR , Design IP , extended long reach , 112g , 112G-ELR

PCB解析／ICパッケージ解析

PCIe開発の歴史: バージョン6への移行

PCIe（Peripheral Component Interconnect Express）は、初期のPCIバスのアップグレードバージョンです。PCIはIntelによって開発され…

• 1 min read
Sigrity and Systems Analysis , PCIe , Sigrity , japanese blog

Breakfast Bytes

Supernaturally Fast Sorting

When I was in my mid-teens, I was writing a program (in FORTRAN) that required me…

• 7 min read
vlsi technology , quicksort , timsort , sorting

Spotlight Taiwan

2021 CadenceLIVE Taiwan系統設計與分析(System Design and Analysis) 助力系統設計研發戰力

隨著5G、AI、工業物聯網（IIoT）、自駕車和超大規模（hyperscale）運算等技術的需求，電子設計也朝更高整合度和多樣化垂直應用發展，為半導體產業帶來了新商機…

• less than a min read
celsius , system analysis , cadencelive taiwan , taiwanese blog , clarity

Breakfast Bytes

Tempus: Design Robustness

The latest release of the Tempus Timing Signoff Solution, 21.1, contains a lot of…

• 4 min read
Tempus , static timing , timing signoff

System, PCB, & Package Design 

ASCENT: Team Collaboration in Allegro System Capture

I know it and you know it. Electronic design cycles are a challenge. All that back…

• 2 min read
17.4 , Team design , 17.4-2019 , Allegro System Capture , ASCENT , team collaboration

Breakfast Bytes

Sunday Brunch Video for 26th September 2021

https://youtu.be/Ivi2dTIcm9E Made at my garden gate (camera Carey Guo) Monday: Ten…

• less than a min read

PCB、IC封装：设计与仿真分析

如何从倒装芯片的角度设计封装

本文作者：Tyler Lockman，Cadence Software Architect，于加拿大卡尔顿大学获计算机科学学士学位后，在Cadence Allegro产品部门工作超过20年…

• less than a min read
IC , Chinese blog , 17.4 , Allegro Package Designer Plus , BGA , 中文 , 封装设计 , IC封装 , Allegro

Computational Fluid Dynamics

This Week in CFD

It's Friday meaning it's time for another roundup of CFD news and detritus from the…

• less than a min read
CFD , Automotive , Aerospace , Pointwise , jobs , Computational Fluid Dynamics , fluid dynamics , HPC , Mesh Generation , Meshing

Breakfast Bytes

September Update: Ransomware, Apple, Zero Trust, and More

It's only September 24, but this is the last Friday of the month so it's time for…

• 5 min read
Apple , rct , zero trust , designed with cadence , update , ransomeware

RF /マイクロ波設計

μWaveRiders: INTRCONNを使用したシステムレベルでのPCB配線効果のモデリング

Team RF "μWaveRiders" ブログシリーズはCadence AWR RF製品のためのショーケースです。月ごとの話題はCadence AWR Design…

• less than a min read
PCB , RF Simulation , PCB traces , AWR Design Environment , integrated circuiit , INTRCONN , RF design , japanese blog , Visual System Simulator(VSS)
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