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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: EMX Planar 3Dでのポート定義

Virtuoso Meets Maxwell はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
Virtuoso Meets Maxwell , Electromagnetic analysis , EMX , EM Analyis , RF design , ICADVM20.1 , japanese blog , Custom IC Design , Virtuoso Layout Suite EXL

Breakfast Bytes

Dr C.C. Wei's Keynote at TSMC Symposium

At the recent TSMC 2021 Online Technology Symposium, the keynote to open the show…

• 9 min read
TSMC , TSMC Technology Symposium

Digital Design

Have You Encountered Any Error/Warning During Scan Insertion in Genus? Do You Want…

Design for Test (DFT) techniques provide measures to test the manufactured device…

• 1 min read
scan , DFT , Genus , warning , error

Breakfast Bytes

RSAC: The Cryptographers' Panel

The Cryptographers' Panel was moderated by RSA's Zulfikar Ramzan, and featured Ron…

• 10 min read
rsa , rsac , rsac2021 , the cryptographers' panel

Verification

Training Insights — Metastability-Aware Verification: Elevate Your Signoff with JasperGold…

I hope you enjoyed and got good insights about the Cadence® JasperGold® CDC during…

• 2 min read
CDC , RTL designer Signoff , Metastability , JasperGold , verification

Breakfast Bytes

Sunday Brunch Video for 13th June 2021

https://youtu.be/T9V_61_3ZVA Made in San Francisco Botanical Garden (camera Carey…

• less than a min read
sunday brunch

Breakfast Bytes

What Is a System? It's Turtles All the Way Down...or Fleas

According to Steven Hawking, in his book A Brief History of Time, Bertrand Russell…

• 5 min read
system level , system

Computational Fluid Dynamics

Not-to-miss Live Webinars about CFD This Month

In June once more we launch a series of not-to-miss live webinars on various CFD…

• 2 min read
CFD , webinars , Pointwise , Computational Fluid Dynamics , fluid dynamics , CFD Applications , NUMECA , Mesh Generation , Meshing , Omnis

Breakfast Bytes

RSAC: Hacking a Solar Power Controller—And Pretending to Generate a Gigawatt

At the recent RSAC, there was a great presentation by Waylon Grange on hacking the…

• 7 min read
rsac 2021 , security , rsa conference , rsa , embedded security , rsac , cybersecurity

カスタムIC／ミックスシグナル

Virtuosity: What’s New on the Cadence Learning and Support Portal – Virtuoso Layout…

誰もが迅速な解決策を探す目まぐるしく動く世界に対応するには、関連する全ての情報を入手できるワンストップの学習リソースがとても役立ちます。Cadence Learning…

• less than a min read
Virtuoso , Virtuosity , ICADVM20.1 , japanese blog , Custom IC Design , RAKs , Virtuoso Layout Suite , Custom IC , IC6.1.8 , Virtuoso Layout Suite XL

RF /マイクロ波設計

μWaveRiders:コネクテッドカーを駆動する RF/マイクロ波技術

The Team RF "μWaveRiders" ブログシリーズはCadence AWR RF製品のためのショーケースです。月ごとの話題はCadence AWR…

• less than a min read
AWR Design Environment , RF communications , RF design , Radar systems , ADAS , Cadence Intelligent System Design , japanese blog

RF Engineering

μWaveRiders: RF/Microwave Technology Driving the Connected Car

A recently published white paper, RF/Microwave Technology Driving the Connected Car…

• 2 min read
AWR Design Environment , RF communications , RF design , Radar systems , ADAS , Cadence Intelligent System Design

System, PCB, & Package Design 

ASCENT: Some Basic Rules for Design Verification

In part 1 of this blog post, we covered the model-less aspect of Allegro® System…

• 2 min read
17.4 , system reliability , design verification , 17.4-2019 , PCB design , Allegro System Capture , ASCENT , simulation , Schematic

Breakfast Bytes

Allegro X, the Design Platform for the Next Generation of Intelligent System Des…

allegro x system design and pcb design with machine learning and unparalleled pr…

• 2 min read
PCB , machine learning , PCB design , pcb machine learning , allegro x

PCB設計／ICパッケージ設計

ASCENT: Unified Searchを使って最適な部品を見つける

デザインに適した部品を見つけることは、設計作業の中で最も時間がかかるパートだと言う人もいます。もしそうであるならば、必要なものをすばやく見つけるのに有効な、あらゆる援助を利用することが求められます…

• less than a min read
17.4-2019 , Allegro System Capture , japanese blog , Unified Search , ASCENT , Schematic , Allegro

Digital Design

A Proven Way to Simulate High-Frequency Electro-Magnetic Effects Using Quantus Extraction…

Cadence offers multiple electromagnetic (EM) extraction technologies to model the…

• 3 min read
Extraction , quantus rlck , Quantus

Breakfast Bytes

TSMC's 3DFabric

I already wrote about TSMC's advanced-node roadmap in my post TSMC: Advanced Technology…

• 3 min read
CoWoS , packaging , TSMC , TSMC Technology Symposium , InFO , 3dfabric

Computational Fluid Dynamics

This Week in CFD

I hope you didn't think I had forgotten. But last Friday was a tad busy so I didn…

• 1 min read
CFD , Aerospace , Pointwise , Computational Fluid Dynamics , fluid dynamics , CFD Applications , NUMECA , CAE , Mesh Generation , Meshing

Spotlight Taiwan

超大規模資料中心、行動通訊與汽車 推動先進製程節點不斷創新 - 摩爾定律仍加速前行!

原文作者: Cadence資深副總裁暨數位與簽核事業群總經理滕晉慶(Chin-Chi Teng) 原文出處: https://www.linkedin.com/posts…

• less than a min read
3nm , Hyperscalers , Digital Implementation , taiwanese blog
CDNS - Fix Layout Hompage