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Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
Corporate 27 Jul 2026 • 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
Corporate 26 Jul 2026 • 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
Corporate 22 Jul 2026 • 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent

Corporate News

AI Infrastructure Starts Beyond the Chip

Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation…

Corporate
Corporate 15 Jul 2026 • 8 min read
chip , featured , AI infrastructure , agentic ai , packaging
cdns - all_blogs_categories

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Blog - Post List
Latest blogs

Digital Design

Conformal Low Power Verification

Learn to verify low-power designs using Conformal ® Low-Power Verification. We've…

FormerMember 9 Aug 2021 • less than a min read

Computational Fluid Dynamics

Cadence CFD at the SU2 Conference 2021

Last month's SU2 Conference brought together the community of researchers and practitioners…

John Chawner 9 Aug 2021 • 3 min read
CFD , Automotive , T-Rex , Aerospace , Pointwise , automation , Computational Fluid Dynamics , voxels , adaptation , Mesh Generation

定制IC芯片设计

Virtuoso Meets Maxwell: Virtuoso RF Solution快速入门

不同种类的模组设计之间的集成趋势引起了PCB 设计风格的流程正向IC设计风格的流程转变。对于任何一个先进的模组设计流程而言,多芯片封装的跨结构设计和验证都必不可少…

Claudia Roesch 9 Aug 2021 • 1 min read
Rapid Adoption Kit , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF Solution , Virtuoso RF , Layout EXL , Chinese blogs

Breakfast Bytes

Sunday Brunch Video for 8th August 2021

https://youtu.be/_dRTQm0DyG0 Made in New York City (camera Carey Guo) Monday: Intel…

Paul McLellan 8 Aug 2021 • less than a min read
sunday brunch

Computational Fluid Dynamics

This Week in CFD

Welcome to the weekend. It's time for This Week in CFD , all the CFD news that I…

John Chawner 6 Aug 2021 • less than a min read
CFD , Computational Fluid Dynamics , fluid dynamics , CFD Applications

カスタムIC/ミックスシグナル

Virtuosity: 分散型ファームにおけるリソースの最適な利用

読者の皆さん、こんにちは。 ジョブやシミュレーションを実行するために、どれくらいのリソースが必要なのか、誰しも疑問に思ったことがありますよね。これは難しい問題で…

Custom IC Japan 4 Aug 2021 • less than a min read
SGE , Analog Design Environment , LBS , Job Policy , ADE , LSF , Virtuoso , Virtuosity , distributed processing , japanese blog , Custom IC Design , IC6.1.8 , Assembler , ADE Assembler

Breakfast Bytes

Offtopic: Today You, Tomorrow Me

It is the last day before a break and so I write about whatever I feel like. It's…

Paul McLellan 4 Aug 2021 • 7 min read
offtopic

System, PCB, & Package Design 

ASCENT: More Reasons to Move to 17.4-2019 Hotfix 019

Picking up from where we left off in the previous post , let’s look at some more…

Rachna2018 3 Aug 2021 • 4 min read
System Capture , 17.4 , publish for manufacturing , LIVE BOM , 17.4-2019 , Allegro Pulse , hotfix 019 , Allegro System Capture , PLM , web dashboard , ASCENT , Allegro

Breakfast Bytes

The Systems Designer's Guide to...Systems Analysis

There is a new book in the System Designer's Guide to... series, published by i.007e…

Paul McLellan 3 Aug 2021 • 5 min read
featured post , system analysis , electrical analysis , Thermal Analysis

Breakfast Bytes

Intel's Process and Packaging Roadmaps

There are only three companies that are on the real leading edge. As you probably…

Paul McLellan 2 Aug 2021 • 5 min read
Intel , intel 4 , featured post , intel 7 , emib , process roadmap , intel 3 , foveros , intel 20a

Breakfast Bytes

Sunday Brunch Video for 1st August 2021

https://youtu.be/I0AYf5V_irg Made in Long Ridge Open Space Preserve (camera Carey…

Paul McLellan 1 Aug 2021 • less than a min read
sunday brunch

Computational Fluid Dynamics

This Week in CFD

It's a Global Recharge Day here at Cadence so why not get recharged by keeping up…

John Chawner 30 Jul 2021 • 1 min read
CFD , Automotive , Computational Fluid Dynamics , CFD Vision 2030 , CFD Applications

Analog/Custom Design

Spectre Tech Tips: Spectre High Impedance Node Check Overview

Circuit checks enable you to analyze typical design problems, such as high impedance…

Amaninder 29 Jul 2021 • 4 min read
spectre aps , dyn_floatdcpath , dyn_float_tran_stat , dyn_highz , highz , static_highz , Spectre , static checks , spectre x , Design Checks , floating node

System, PCB, & Package Design 

System Analysis Knowledge Bytes: Computational Fluid Dynamics Roundup – July 202…

Welcome to the Computational Fluid Dynamics Roundup series, your monthly roundup…

deeptik 29 Jul 2021 • 5 min read
CFD , System Analysis Knowledge Bytes , Pointwise , Computational Fluid Dynamics , NUMECA , Mesh Generation , Meshing , Omnis

System, PCB, & Package Design 

ASCENT: Reasons to Move to 17.4-2019 Hotfix 019

“The only constant in life is change” nowhere is this adage truer than in the world…

Rachna2018 29 Jul 2021 • 4 min read
17.4 , DRC , logical design , Layout , 17.4-2019 , audit , Allegro System Capture , ASCENT , Schematic , Allegro

System, PCB, & Package Design 

IC Packagers: Reuse Wirebond Placement with Place Replicate Modules

Most package designs have wire bonding and reusing the wire bond information for…

avijeet 29 Jul 2021 • 3 min read
17.4 QIR3 , 17.4 , APD , IC Packaging & SiP design , Allegro Package Designer , 17.4-2019 , ICPackagers

Analog/Custom Design

Virtuosity: More Usability Enhancements in Virtuoso ADE Assembler and Virtuoso ADE…

We've been busy improving the usability of the Analog Design Environment products…

Arja H 29 Jul 2021 • 3 min read
Analog Design Environment , ADE Explorer , designing analog circuits , make editable , run point selection , ADE , variables , Virtuoso Analog Design Environment , analog integrated circuit design , make read-only , analog design , usability , Custom IC Design , ADE Assembler

Computational Fluid Dynamics

Pipistrel Mitigates Aviation Noise Emissions for Electric Aircraft

Pipistrel is a world-leading designer and manufacturer of small aircrafts specializing…

AnneMarie CFD 29 Jul 2021 • 1 min read
Aerospace , aviation sustainability , fluid dynamics , green aviation , Aerospace Engineering , simulation software , Noise Reduction

Breakfast Bytes

Offtopic: Immersive Vincent van Gogh

Cadence has a global holiday tomorrow and Breakfast Bytes will not appear. Back on…

Paul McLellan 29 Jul 2021 • 8 min read
offtopic , van gogh , immersive van gogh
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CDNS - Fix Layout Hompage

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