Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

IC Packagers: How to Quickly Push Design Connectivity across a Design

The task of IC/package co-design causes multiple challenges during the design cycle…

• 4 min read
17.4 , IC Packaging and SiP , IC Packagers , Allegro Package Designer , 17.4-2019 , PCB design

Analog/Custom Design

Virtuoso ICADVM20.1 ISR17 and IC6.1.8 ISR17 Now Available

The ICADVM20.1 ISR17 and IC6.1.8 ISR17 production releases are now available for…

• 4 min read
Cadence blogs , ADE Explorer , cadence , Virtuoso RF Solution , IC Release Announcement blog , Virtuoso Analog Design Environment , ICADVM20.1 , IC Release Blog , Clarity 3D Solver , Custom IC Design , Virtuoso Layout Suite EXL , Virtuoso Layout Suite , Custom IC , ADE Verifier , IC6.1.8 , ADE Assembler

Spotlight Taiwan

Sigrity X 2021 盛裝登場!

原文出處: Announcing Sigrity X 作者: Paul McLellan 在EDA領域中運用了許多不同的運算軟體。然而EDA產業所面臨的挑戰在於…

• less than a min read
Chinese blog , Sigrity X , Signal Integrity , taiwanese blog

Breakfast Bytes

Verilog HDL and Its Ancestors and Descendants

Most conferences take place annually, or in some cases every two years. The History…

• 8 min read
SystemVerilog , Superlog , HILO , Verilog , dcvon 2021 , Imperas , DVcon , Co-Design Automation

Verification

Verifying Protocol Tunneling with Cadence USB4 VIP — The Multiprotocol Advantage

All the workings of USB4 protocol are primarily about how to transfer the native…

• 1 min read
Verification IP , USB4 VIP , DisplayPort , usb4 , PCIe , Protocol Tunneling , usb4 router , USB3

Digital Design

iSpatial: Next-Generation Common Physical Optimization Flow

With advanced-process nodes, a standard cell's physical delay, net delay, and congestion…

• 1 min read
Genus , Logic Design , Synthesis , ispatial , physical implementation

Breakfast Bytes

DeepChip Best of 2020: Xcelium ML

Recently, I wrote about #2a on Cooley's Best of 2020 list, which was Cadence's vManager…

• 3 min read
deepchip , xcelium ml , john cooley , verification

Breakfast Bytes

Sunday Brunch Video for 21st March 2021

https://youtu.be/i96zZHBFnTQ Made in my kitchen (camera Ziyue Zhang) Monday: The…

• less than a min read
sunday brunch

System, PCB, & Package Design 

BoardSurfers: How to Create and Remove External DRCs using SKILL in PCB Editor

Design rules checks (DRC) determines whether your layout design complies with design…

• 4 min read
17.4 , PCB design and layout , 17.4-2019 , PCB design , Allegro PCB Editor , SKILL

Breakfast Bytes

Offtopic: Man Wife Lung Slices (夫妻肺片)

Tomorrow is a Cadence global holiday. That's what it sounds like. Breakfast Bytes…

• 6 min read
offtopic

PCB解析／ICパッケージ解析

Sigrity / Systems Analysis 2021.1 リリース(2021年2月) - 新機能ハイライト

SIGRITY から SIGRITY/SYSANLSへのリネーム SIGRITYリリースは、これからはSIGERITY/SYSANLSという名称で呼ばれることになります…

• 1 min read
Sigrity and Systems Analysis , Celsius Thermal Solver , celsius , Clarity 3D Transient Solver , OrCAD/Allegro 17.4 (SPB174) , Sigrity , japanese blog , Sigrity 2021.1 , Clarity 3D Solver , Layout Workbench , clarity

カスタムIC／ミックスシグナル

Spectre Tech Tips: Spectre XDP-HB (Distributed HB) のご紹介

SPECTER 20.1.ISR4以降のリリースでは、新しいSpectre® X-RFシミュレーションテクノロジーの一部としてSpectre XDP-HBがリリースされました…

• less than a min read
Spectre RF , Spectre XDP-HB , Spectre X-RF , japanese blog , Spectre X distributed simulation

RF /マイクロ波設計

μWaveRiders:RF /マイクロ波の学生様向けCadence AWRの大学プログラム

Team RF "μWaveRiders" ブログシリーズがCadence AWR RF製品のためのショーケースとしてデビューします。月ごとの話題はCadence…

• less than a min read
microwave , RF , AWR Analyst , Cadence Academic Network , AWR Design Environment , AWR AXIEM , RF design , AWR VSS , japanese blog , university program

RF Engineering

μWaveRiders: Cadence AWR University Program for RF/Microwave Students

For students in the RF/Microwave area of study, the Cadence AWR Design Environment…

• 4 min read
microwave , RF , AWR Analyst , Cadence Academic Network , AWR Design Environment , AWR AXIEM , RF design , AWR VSS , university program

Computational Fluid Dynamics

ETNZ Wins the America's Cup Once Again Using FINE/Marine

Once again Emirates Team New Zealand has entered the history books and won the America…

• less than a min read
CFD , fine/marine , Computational Fluid Dynamics , NUMECA

Breakfast Bytes

DeepChip Best of 2020: vManager

We just finished 2020 (and let's hope 2021 is a better year). Every year, John Cooley…

• 4 min read
deepchip , john cooley , vManager , verification

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: Virtuoso RF ソリューション — フローの革命が次のレベルへ突入

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
5G , IMS , integrand , SiP , pegusas , Virtuoso Overture , VRF , Celcius , awr , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF , Allegro Package Designer Plus , EMX , AWR AXIEM , RF design , SiP Layout Option , ICADVM20.1 , Sigrity , japanese blog , Quantus , Clarity 3D Solver , Custom IC Design , Allegro , VMM

Analog/Custom Design

Virtuoso Meets Maxwell: How to Simulate an RF Block with Passive and Active Devices…

Do you work with RF designs that contain both active and passive devices? Have you…

• 3 min read
AXIEM , VLS EXL , EM Solver , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Electromagnetic analysis , black boxing , Virtuoso , EMX , ICADVM20.1 , Clarity 3D Solver , Virtuoso Layout Suite EXL

Breakfast Bytes

Announcing Sigrity X

There are many different computational software algorithms used in EDA. One challenge…

• 6 min read
x-technology , computational software , Signal Integrity , Sigrity
CDNS - Fix Layout Hompage