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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

カスタムIC／ミックスシグナル

Start Your Engines: Spectre Xシミュレータでアナログ・ミックスシグナル検証を高速化する

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により…

• 1 min read
spectrex , AMS Designer , universal verification methodology , analog/mixed-signal , axum , japanese blog , mixed-signal design , AMSD Flexible , mixed-signal verification , AMS Flex

System, PCB, & Package Design 

IC Packagers: How to Define Your Own Team-Certified Wire Profiles

Back at the start of 2020, we talked about why you shouldn't use the default wire…

• 4 min read
IC Packaging & SiP design , Allegro Package Designer , 17.4-2019

Analog/Custom Design

Virtuoso Meets Maxwell: Enabling System Analysis And Implementation Through Libr…

Welcome to a post on how to create component and padstack libraries for use in the…

• 4 min read
Technology Independent Layout Pcell , Unified Library , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF Solution , Virtuoso RF , Virtuoso MultiTech , Electromagnetic analysis , librarian , SiP Layout Option , ICADVM20.1 , Cadence SiP Layout , TILP , Custom IC Design , VMM

System, PCB, & Package Design 

(P)SpiceItUp: Verifying and Optimizing Designs with PSpice A/D

PSpice® A/D is a fully featured analog and mixed-signal simulator that can be integrated…

• 4 min read
17.4 , OrCAD Capture , PSpiceA/D , Capture CIS , PSPICE , 17.4-2019

Academic Network

Become a Cadence Academic Network Certified Instructor!

Are you a lab instructor sitting at home right now? Have you completed some Cadence…

• 2 min read
Cadence Academic Network , Certified Lab , academia , Gdansk , online training

Analog/Custom Design

Virtuosity: Conserve Power—Importing and Exporting Power Intent

In this blog, I will focus on the key enablers, which are required before the power…

• 6 min read
Virtuoso Schematic Editor , virtuoso power manager , Conformal Low Power , VPM , Supply States , 1801 , setup , Virtuoso , Virtuosity , ICADVM20.1 , UPF , IEEE , mixed-signal design , Liberty , Custom IC Design , power domains

Breakfast Bytes

Thanksgiving Off-Topic: Edelweiss

It's Thanksgiving next week in the U.S. I am taking the whole week off and Breakfast…

• 6 min read
offtopic

カスタムIC／ミックスシグナル

Spectre Tech Tips: Spectre X アップデート

およそ1年前、SPECTRE 19.1 baseリリースにてSpectre Xシミュレータをリリースしました。それ以来、後続のSPECTRE 19.1 ISRリリースでのSpectre…

• less than a min read
+preset , LX mode , Distributed HB , japanese blog , XDP , spectre x

Analog/Custom Design

Start Your Engines: Mixed-Signal Modeling Methods for Converting an Electrical Signal…

This blog explains how to convert an electrical signal to a real number in your design…

• 5 min read
real number modeling , electrical to real conversion , AMS-Designer , Start Your Engines , analog/mixed-signal , mixed signal , mixed-signal verification

Digital Design

Library Characterization Tidbits: Rewind and Replay - 3

This blog provides a summary of the last five blogs posted in the Library Characterization…

• 2 min read
constraint probes , minimum period arc , Liberate LV , encounter , library characterization , Liberate MX , Library Characterization Tidbit , Digital Implementation , Liberate Characterization Portfolio , library validation

Breakfast Bytes

RISC-V Summit 2020 Preview

The third of three events taking place in the first three weeks of December is the…

• 4 min read
risc-v

Breakfast Bytes

IEDM 2020 Preview

Every December is the IEEE International Electron Devices Meeting (IEDM). The somewhat…

• 5 min read
iedm 2020 , IEDM

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: Virtuoso RF Solutionのクイックスタート

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
Rapid Adoption Kit , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF Solution , Virtuoso RF , Layout EXL , Virtuoso MultiTech , ICADVM20.1 , Cadence SiP Layout , japanese blog , Custom IC Design , RAKs , Allegro , VMM

System, PCB, & Package Design 

IC Packagers: Why You Can’t Start a Co-Design Die in Allegro Package Designer

Let’s investigate this question today, as I’ve been asked a few times over the years…

• 4 min read
IC Packaging & SiP design , Allegro Package Designer , 17.4-2019

Analog/Custom Design

Virtuosity: Decoding the Mechanics of What If in Voltus-Fi-XL

What if you could foresee potential changes in your design and analyze their impact…

• 4 min read
EMIR Analysis , debug , Voltus-Fi-XL , what-if analysis , Virtuoso , Virtuosity , ICADVM20.1 , Custom IC Design , IC6.1.8 , EMIR

Breakfast Bytes

WEAA EDA/IP Product of the Year: Digital Full Flow with iSpatial Technology

Aspencore Media, the publishing house that owns EDN (where I first started blogging…

• 3 min read
EDN , EETimes , digital full flow , aspencore media , ispatial

カスタムIC／ミックスシグナル

Start Your Engines: AMS Designerのローパワー・ミックスシグナル・シミュレーションにおける２つの重要なコンポーネント

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により…

• less than a min read
AMS Designer , mixed-signal simulation , Mixed-Signal , low-power design , Connect Module , japanese blog , low power format

Breakfast Bytes

Cadence 5th Annual Photonics Event

Coming up on December 1 - 3 is the 5th annual Cadence Photonics event, although it…

• 2 min read
HPC , photonics

Breakfast Bytes

Cadence Cloud: The Video Version

Recently, Cadence released a series of videos about all the various aspects of Cadence…

• 2 min read
cloudburst , cadence cloud
CDNS - Fix Layout Hompage