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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

Breakfast Bytes

Automotive Ethernet

Automotive networking is perhaps the latest application area for Ethernet. But Ethernet…

• 6 min read
Automotive , Design IP , Ethernet

System, PCB, & Package Design 

BoardSurfers: Allegro In-Design Coupling Analysis: Crosstalk Mitigation without …

Just as social distancing minimizes human contact to prevent the spread of disease…

• 2 min read
PCB SI , PCB design , Allegro

System, PCB, & Package Design 

IC Packagers: Keep Fan-Out Routing Aligned During ECOs

When a change comes in from your IC design partner, it can be met with trepidation…

• 4 min read
Allegro Package Designer

Breakfast Bytes

Simon Butler's Fireside Chat with Jim Hogan

Way back in what now seems like the distant past, but was early March, I wrote a…

• 8 min read
Design IP , Simon Butler , Methodics , Jim Hogan , esd alliance

Analog/Custom Design

Virtuoso Meets Maxwell: How to Route a Package in Virtuoso?

Let’s explore how a package design looks like in Virtuoso, how it can handle planes…

• 5 min read
shove , ICADVM18.1 , route a package , push , Virtuoso Layout EXL , Virtuoso Meets Maxwell , route , Virtuoso RF Solution , Virtuoso RF , Layout EXL , Package Design in Virtuoso , system design , RF design , push and shove , Custom IC Design , Custom IC

Breakfast Bytes

Sunday Brunch Video for 24th May 2020

www.youtube.com/watch Made in "Hawaii" (camera Carey Guo) Monday: Which Passwords…

• less than a min read
sunday brunch

Analog/Custom Design

Start Your Engines: The Why and How of Generating Spectre Netlists for Analog Blocks…

Read to know about generating netlist in the Spectre native format using AMS UNL…

• 3 min read
AMS Designer , Unified Netlister , analog/mixed-signal , mixed signal , AMS UNL , mixed-signal verification

System, PCB, & Package Design 

BoardSurfers: Footprint Creation Using a STEP Model in Library Creator

Read how you can easily create accurate footprints from a vendor-provided STEP Model…

• 3 min read
Library Creator , PCB Editor , 17.4-2019 , ECAD-MCAD Library Creator , PCB design , Allegro

Breakfast Bytes

Memorial Day: Conway and Collatz

Do you know what the Collatz Conjecture is? John Horton Conway died recently, as…

• 6 min read
offtopic

Breakfast Bytes

It's the Second Mouse That Gets the Cheese

I love short phrases that make you think, "Wait...what?" and then you think about…

• 7 min read
late to market , moat , early to market , barriers to entry , startup

System, PCB, & Package Design 

IC Packagers: Determining Minimum Spacing Values in a Design

I don’t remember the first time I was asked this question. At its core, the question…

• 4 min read
Allegro Package Designer

Breakfast Bytes

A History of Neural Networks

Research on biological neurons started back in the 1940s, before computers, and long…

• 8 min read
featured , neural networks , AI , neural nets

Verification

Interconnect Beyond PCIe: CXL and Cache Coherent Interconnect

As the de facto IO interconnect technology, PCIe has commendably addressed the performance…

• 2 min read
Verification IP , VIP , PCIe , Internet of Things , Denali , PCI Express , verification

Academic Network

Learning in a Virtual World

The Cadence Academic Network enables you to access Cadence tools remotely, and, in…

• 3 min read
Europractice , Cadence Academic Network , remote learning , CMC Microsystems , online learning

Analog/Custom Design

Virtuosity: Rewind and Replay the Top 10 Cadence Virtuosity and Virtuoso Video Diary…

With new content being posted nearly every week under Custom IC Design Blogs, there…

• 3 min read
Analog Design Environment , Cadence blogs , ICADVM18.1 , ADE Explorer , Virtuoso Space-based Router , MODGEN , Auto Place and Route , System Design Platform , APR , Layout , Virtuoso , Virtuosity , Virtuoso Layout Suite , Custom IC , simulation , IC6.1.8 , ADE Assembler , MTS

定制IC芯片设计

Virtuoso Meets Maxwell：Virtuoso射频解决方案——流程一体化的技术改革

我刚刚从马萨诸塞州的波士顿，这个极具革命盛名的地方回到家，在那我参加了2019国际微波大会（IMS 2019）。今年峰会很精彩，不仅因为波士顿风景迷人，更因为这里是…

• less than a min read
Chinese blog , Cadence blogs , ICADVM18.1 , VRF , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Layout EXL , virtuoso system design platform , Virtuoso , Allegro

Breakfast Bytes

Which Passwords Should You Change?

I was talking to someone who consults to Cadence on various aspects of security.…

• 9 min read
security , tfa , password , two-factor authentication

Breakfast Bytes

Sunday Brunch Video for 17th May 2020

https://youtu.be/We9eDDOn-Cg Made in "Instanbul" (camera Carey Guo) Monday: Why…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

极致PCB设计全流程 I 技巧三：规则管理器应用技巧

本期技巧篇内容与大家分享规则管理器（Allegro® Constraint Manager，简称CM）中输入数据的几个细节操作以及“信号不允许表层布线”的规则设置…

• less than a min read
设计经验 , Chinese blog , 软件技巧 , training , webinar , PCB设计 , 中文 , 直播网课 , online training , Allegro , 专家培训
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