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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

Implementing Arm Hercules with Digital Full Flow

At Arm TechCon, there was a joint presentation by Arm, Cadence, and Samsung Foundry…

• 3 min read
Genus , hercules , Samsung , Innovus , ARM , full flow

Digital Design

Library Characterization Tidbits: Basics of Standard Cell Characterization and M…

Characterization of standard cell libraries using the Liberate Characterization solution…

• 2 min read
tidbits , SPICE netlist , Standard Cell , characterization , Liberty Files , Spectre , Library Characterization Tidbit , Digital Implementation , Characterization Solution , Liberate , Inside-View , Liberate Characterization Portfolio , Rapid Adoption Kits , ECSM , RAKs , CCS , Model Files

Breakfast Bytes

2nd WOSET Workshop on Open-Source EDA

During ICCAD earlier in the month, there was the 2nd WOSET, which stands for Workshop…

• 4 min read
open source eda , openroad , woset

System, PCB, & Package Design 

IC Packagers: A Cross-Section of Changes

While 17.4 has only been amongst you for a month, now, I’ve had a few questions regarding…

• 3 min read
APD

System, PCB, & Package Design 

BoardSurfers: Power of Information – Quickly Getting Started with Allegro and OrCAD…

The Allegro and OrCAD 7.4 release is now available for download and installation…

• 1 min read
COS , System Capture , IC Packaging , Cadence Online Support , PSPICE , PCB Editor , Design Entry HDL , EDM , 17.4-2019

Breakfast Bytes

Verifying Processor Security, Part 2

This is the second post about Eli Singerman's keynote at the recent Jasper User Group…

• 5 min read
Jasper User Group , formal , Jasper , JasperGold , Formal verification

Analog/Custom Design

Virtuoso Meets Maxwell: Package PDK in Virtuoso! How Is It Even Possible? (Part 2…

Alright… I’m back again to amuse you with another part on how to set up Package PDK…

• 4 min read
SiP , ICADVM18.1 , Virtuoso Meets Maxwell , Virtuoso RF , Layout EXL , Package Design in Virtuoso , Layout , Virtuoso , System Design Environment , RF design , Modeling , Custom IC Design , Virtuoso Layout Suite , Custom IC , Allegro

Breakfast Bytes

Formally Verifying Processor Security

Intel has had a couple of major events that totally changed their attitude to verification…

• 4 min read
Intel , Jasper User Group , formal , Jasper , JasperGold

PCB、IC封装：设计与仿真分析

RF设计直播课程：如何提高RF前端模块封装设计的迭代效率

大家好，我是Principal Customer Engagement Engineer江亮，从事射频前端模块设计七年，先后受聘于Qorvo，RDA等多家射频半导体研发企业…

• less than a min read
PCB , RF , Chinese blog , PCB设计 , 封装设计 , 直播网课 , 射频前端 , Sigrity , Allegro , 专家培训

Academic Network

CADathlon at ICCAD 2019

Last week, I visited the Cadathlon@ICCAD event at the 2019 International Conference…

• 2 min read

System, PCB, & Package Design 

BoardSurfers: What's Happening Around 17.4-2019?

Allegro and OrCAD 17.4-2019 was released on October 18 and we have since then been…

• 2 min read
17.4 , PCB Editor , SKILL

Breakfast Bytes

OpenROAD: Open-Source EDA from RTL to GDSII

OpenROAD is a DARPA program to attempt to build a no-human-in-the-loop EDA flow,…

• 6 min read
ucsd , dod , openroad , andrew kahng , darpa

Academic Network

Successful Speaker Event—Engaging with Professor in Shanghai

The Cadence Academic Network hosted an Academic Speaker Series event, in collaboration…

• 2 min read
university , Cadence Academic Network , academia , university program

Breakfast Bytes

What Does P≠NP Mean?

Recently I wrote about computational software and said that EDA algorithms are all…

• 6 min read
NP-complete , computational software , np-hard

Analog/Custom Design

Virtuosity: Usability Enhancements in the Property Editor

Goes without saying that the Property Editor is the most frequently used feature…

• 2 min read
ICADVM18.1 , Virtuoso Layout Suite L , Property Editor , Custom IC Design , Virtuoso Layout Suite , IC6.1.8

Breakfast Bytes

Die-to-Die Interconnect: The UltraLink D2D PHY IP

One of the big trends that has been happening somewhat below the radar is the growth…

• 5 min read
system in package , SiP , chiplet , more than Moore , 3D packaging

System, PCB, & Package Design 

IC Packagers: Plan Your Escape with Modernized Structures

Many of you, our regular readers, are familiar with via structures. These reusable…

• 3 min read
17.4 , APD

Life at Cadence

Asking Our Employees: What Makes Us Great in Europe?

As the project manager of our global Great Place to Work programs, I’ve had the opportunity…

• 6 min read
Culture , Community , giving back , GPTW , great place to work

Analog/Custom Design

Virtuoso Meets Maxwell: Help With Electromagnetic Analysis - Part III

This is the third blog in the multi-part series that aims at providing in-depth details…

• 8 min read
ICADVM18.1 , Virtuoso Layout EXL , Virtuoso RF , Layout EXL , Electromagnetic analysis , Virtuoso , Custom IC Design
CDNS - Fix Layout Hompage