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Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate
• 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

Ludwigsburg: It's All About Return-on-Investment

I attended the Automobil Elektronik Kongress at Ludwigsburg outside Stuttgart. it…

• 6 min read
Automotive , Automotiv Elektronik Kongress , ludwigsburg , ADAS

Breakfast Bytes

Sunday Brunch Video for 28th July 2019

https://youtu.be/-36euXtgU7Y Made at Cadence Summer of Love Party (camera Chad Yee…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

开放注册：2019 Cadence中国用户大会

Cadence中国用户大会 CDNLive China 2019 上海浦东嘉里大酒店 - 2019年8月15日星期四 space 亲爱的用户朋友： 一年一度的Cadence全球用户大会CDNLive…

• less than a min read
PCB , Chinese blog , CDNLive , CDNLive 2019 , 中文 , cdnlive china , Sigrity , 中国用户大会 , Allegro

System, PCB, & Package Design 

BoardSurfers: Designing a Rigid-Flex Board Using PCB Editor

Whether you are designing the latest pace-maker or a LED strip, you have definitely…

• 4 min read
PCB Editor , Rigid-Flex

Breakfast Bytes

Digital Twins at the Paris Air Show

The idea of a digital twin should be easy for anyone in aerospace to understand.…

• 5 min read
Aerospace , Protium , Palladium , digital twin , paris air show , verification

Breakfast Bytes

Galileo Down for a Week

You might never have heard of Galileo, the European Union's GNSS, or Global Navigation…

• 4 min read
Galileo , GPS , mobile

Computational Fluid Dynamics

Honda Demonstrates a Major Breakthrough in Meshing Speed with AutoSeal and Hexpr…

Authors: Akio Takamura, Chief Engineer, Honda R&D, and Benoit Mallol, Head of Marine…

• 3 min read
CFD , Automotive , Computational Fluid Dynamics , fluid dynamics , Meshing , simulation

定制IC芯片设计

Virtuoso 视频日记: 下一件大事 - ADE Verifier与Cadence vManager合作

今天的博客重点介绍了ADE Verifier的最新增强功能。这个博客我们每周二和周四发布的迷你博客系列的一部分，以涵盖 Virtuoso®ADE Assembler…

• 1 min read
verifier , Chinese blog , ICADVM18.1 , Functional Verification , Formalized Verification , vPlan , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso Video Diary , ADE Blog Series , mixed signal , mixed-signal design , Custom IC Design , Custom IC , ADE Verifier , IC6.1.8 , vManager , verification

Verification

Tales from DAC: Semiconductor Design in MY Cloud? It's More Likely Than You Thin…

Everyone keeps talking about “the cloud” this and “the cloud” that these days—but…

• 2 min read
DAC 2019 , Semiconductor , cadence cloud

Analog/Custom Design

Virtuosity: bindStrict or Not in Virtuoso in the Times of Chandrayaan 2

Really, can Virtuoso bind strict? And what does that mean? Read along to find out…

• 2 min read
Update Binding , ICADVM18.1 , Layout XL Environment Variables , cdsenv , Virtuoso , Check Against Source , bindStrict , Custom IC Design , Update Components And Nets , Binder , IC6.1.8 , Virtuoso Layout Suite XL , binding

Breakfast Bytes

Computer Scientist Alan Turing to Be on British £50 Note

Last week the Bank of England announced that the new £50 note will have Alan Turing…

• 7 min read
bletchley park , turing award , alan turing

Whiteboard Wednesdays

Whiteboard Wednesdays – The Storage Combo PHY IP – Nirvana!

In this week’s Whiteboard Wednesdays video, Jacek Duda describes three storage protocols…

• less than a min read
Whiteboard Wednesdays , PHY IP , ONFI 4.x

Breakfast Bytes

Virtuoso Meets Maxwell

When I was a postgraduate at Edinburgh University, my office was in the James Clerk…

• 3 min read
RF , maxwell , Virtuoso

System, PCB, & Package Design 

IC Packagers: Correcting Die Orientations and Die Attachments

When you add a die component to your SiP Layout design, you must identify both its…

• 3 min read
APD , SiP Layout

定制IC芯片设计

Virtuosity: 我的 Checks 通过还是没有运行？

今天的博客重点介绍 Checks/Asserts 结果显示和 Summary 表。 这个博客是我们每周发布两次 - 周二和周四 - 的迷你博客系列的一部分，以涵盖…

• 1 min read
Chinese blog , ADE Explorer , Virtuosity , Custom IC Design , ADE Assembler

Analog/Custom Design

Tales from DAC: MediaTek's Experience with Spectre X Simulator

MediaTek recently gave the new Spectre X Simulator a try, and they talked about their…

• 1 min read
Cadence Theater , DAC 2019 , mediatek , spectre x

System, PCB, & Package Design 

DATA Pulse: In Search of the Perfect Environment—Configuring Allegro EDM

Ah, the office temperature – that eternal debate. As in many offices, ours has some…

• 2 min read
allegro edm , PCB design

Analog/Custom Design

Virtuoso Meets Maxwell: Export the Die? What Am I Exporting? To Where?

Here I come back with another episode of TILP of the Virtuoso Meets Maxwell series…

• 4 min read
ICADVM18.1 , die export , Virtuoso Meets Maxwell , Virtuoso RF , die , Layout , Multitech , TILP , Custom IC Design , Virtuoso Layout Suite

Breakfast Bytes

Passwords and Multi-Factor Authentication

I recently came across an interesting piece written by Microsoft's Alex Weinert,…

• 6 min read
security , passwords , two factor authentication
CDNS - Fix Layout Hompage