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Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate
• 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent
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Blog - Post List
Latest blogs

Breakfast Bytes

MWC Part Dos

Yesterday I wrote my first post about MWC19 Barcelona . Today is the continuation…

• 8 min read
5G , MWC , daimler , BMW , ARM

Breakfast Bytes

MWC Barcelona

Last week it was MWC Barcelona. As seems to be the fashion, like with CES, MWC just…

• 7 min read
5G , gsma , MWC , mobile , vodaphone

Breakfast Bytes

Sunday Brunch Video for 4th March 2019

https://youtu.be/wjX4hOvb9-I Made at MWC19 Barcelona (camera JD Estella) Monday…

• less than a min read
Automotive , connx b20 , lidar , mwc19 , radar , MWC , 112g , v2x , SerDes , mobile , bitcoin , Sigrity , ARM , Breakfast Bytes , blockchain

PCB、IC封装：设计与仿真分析

Allegro PCB Editor: 进阶使用技巧

本文将和大家分享Allegro PCB Editor的进阶使用技巧，旨在利用快捷键操作而减少鼠标点击次数，同时包含了定制特定的应用环境，让工具发挥最大效率的方法和示例…

• less than a min read
Chinese blog , 软件技巧 , PCB设计 , 中文 , Allegro PCB Editor , Allegro PCB编辑器 , Allegro

Breakfast Bytes

Who Is Satoshi Nakamoto?

Nobody knows. Really. Here's what is known. He (or maybe it's she or they) is the…

• 8 min read
satoshi nakamoto , cyptography , bitcoin , blockchain

Life at Cadence

International Women's Day

Cadence hosts Girls Who Code founder and CEO Reshma Saujani for talk Cadence is…

FormerMember • 1 min read
Insights on Culture , STEM , Women's Day , Reshma Saujani , International Women's Day

Breakfast Bytes

Signal Integrity for 112G

At DesignCon at the end of January, a team from Cadence presented to a standing-room…

• 5 min read
AMI , pam4 , 112Gbps , 112g , SerDes , Sigrity , SystemSI

Analog/Custom Design

Spectre Tech Tips: Device Aging? Yes, even Silicon wears out

While most of us would like our electronic gadgets to last forever, the reality is…

• 3 min read
Stress Analysis , TDDB , PBTI , native reliability analysis , Spectre , reliability analysis , HCI , NBTI , reliability

Breakfast Bytes

DesignCon: 5G for V2X Communication

One of the keynotes at the recent DesignCon was by Robert Heath of UT Austin titled…

• 5 min read
5G , Automotive , DesignCon

Whiteboard Wednesdays

Whiteboard Wednesdays - Evolution of the ConnX Family with B10 and B20

In this week’s Whiteboard Wednesdays, Pierre-Xavier Thomas introduces the B10 and…

• less than a min read
Whiteboard Wednesdays , ConnX

Analog/Custom Design

Virtuosity: New Flexible Subwindows

Plots in Cadence Virtuoso Visualization and Analysis can be plotted in a window or…

• 3 min read
ICADVM18.1 , subwindows , waveforms , Virtuoso Analog Design Environment , ViVA , Virtuosity , plotting templates , Custom IC Design , IC6.1.8

Breakfast Bytes

Tensilica ConnX B20 for 5G, and Automotive Radar/Lidar

I'm sure you've noticed that there is a lot of talk about 5G in the air. Well, "in…

• 6 min read
5G , connx b20 , lidar , radar , Tensilica

The India Circuit

Opportunities for India in Industry 4.0

The India Electronics and Semiconductor Association (IESA) the industry body that…

• 3 min read
Vision Summit , Industry 4.0 , gig economy , IESA

Breakfast Bytes

OFC: The Optical Fiber Communication Conference

OFC is the Optical Fiber Communication Conference and Exposition (yes, some initials…

• 3 min read
optical fiber , photonics

Breakfast Bytes

Sunday Brunch Video for 24th February 2019

https://youtu.be/uUWiysEM4jM Made on the top of building 10 (camera Sean) Monday…

• less than a min read
sunday brunch , video

PCB、IC封装：设计与仿真分析

DesignCon：Cadence与IBM联手讲授高级IBIS-AMI技术

本文翻译自Cadence "Breakfast Bytes" 专栏作者Paul McLellan文章 "DesignCon: Cadence teaches AMI…

• less than a min read
Chinese blog , DesignCon , AMI , IBIS , IBIS-AMI , 中文 , SerDes , Sigrity

Breakfast Bytes

Badges—Not Just for Scouts Anymore

Were you a Boy Scout? Or a Girl Guide or Girl Scout? What badges did you earn? Not…

• 3 min read
digital badge , training , training bytes

System, PCB, & Package Design 

Simulation of LPDDR4X Interface: What Designers Need to Know and Do

System designers are familiar with standard DDR4 RAM components but with the demands…

• 2 min read
Serial link analysis , SI , LPDDR4 , DesignCon , DesignCon 2019 , Signal Integrity , Channel simulation , Sigrity , BER , SystemSI

Analog/Custom Design

Verifying Power Intent in Analog and Mixed-Signal Designs Using Formal Methods

Analog and Mixed-signal (AMS) designs are increasingly using active power management…

• 2 min read
AMS , Virtuoso Schematic Editor , Low Power , virtuoso power manager , Virtuoso-AMS , mixed signal design , mixed signal solution , Virtuoso , low-power design , mixed signal , mixed-signal verification
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