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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

System, PCB, & Package Design 

What's Good About the Latest in ADW? The 16.6-2015 Release Has Several New Enhancements…

With the Allegro Design Workbench (ADW) 16.6-2015 release, you’ll have several new…

• 2 min read
PCB , Cadence Design Systems , Allegro Design Workbench , Library and design data management , Grzenia , Librarians , library , ADW

Breakfast Bytes

Andrew Kahng on Industry-Academia Cooperation

At CDNLive Silicon Valley, Professor Andrew Kahng of UCSD gave a presentation titled…

• 4 min read
ucsd , Cadence Academic Network , CDNLive , academia , kahng , CDNLive Silicon Valley

SoC and IP

Continued Strength of the Design&Reuse IP-SoC India

Design&Reuse events are always exciting for their draw of an IP-centric audience…

• 1 min read
PCIe Gen4 , 10G-KR , SerDes

Verification

Simulation Acceleration—Maximizing Simulator Performance

"Simulation Acceleration” or “Accelerated Verification” are terms commonly used to…

• 4 min read
Specman , Functional Verification , e , specman elite , verification

Whiteboard Wednesdays

Whiteboard Wednesdays—Creating an Acceleration-Ready Simulation Environment with…

In this week's Whiteboard Wednesdays video, Ofer Steinberg explains how accelerated…

• less than a min read
accelerated VIP , Verification IP , Whiteboard Wednesdays , IP , VIP , Palladium XP , simulation , SystemVerilog UVM , verification

Breakfast Bytes

CDNLive: Routing at 10nm

At CDNLive Silicon Valley, Geeta Garg and Chad Hale of ARM, and Ming Yue of Cadence…

• 3 min read
CDNLive , Routing , implementation , 10nm

Breakfast Bytes

What Is RocketSim? Why Did Cadence Acquire Rocketick?

I talked to Uri Tal last week, who has just joined Cadence as a result of the Rocketick…

• 3 min read
dac2016 , gate-level simulation , DAC , Functional Verification , NVIDIA , RTL simulation , Incisive , dft simulation , rocketick , rocketsim , intel capital , Breakfast Bytes

Breakfast Bytes

Linley IoT Conference: Security and...Well, Just Security

Mike Demler gave the keynote at the Linley IoT conference a couple of weeks ago.…

• 5 min read
security , IoT , industrial , Linley , wearables , Internet of Things , power , consumer , Breakfast Bytes

Breakfast Bytes

It's HOT in Austin in June

Every DAC, Heart of Technology (HOT) organizes an event. This year it will be held…

• 2 min read
dac2016 , DAC , CASEA , HOT , Heart of Technology , Jim Hogan , Breakfast Bytes

Breakfast Bytes

Party Like It's 1999—How the Denali Party Started

As everyone in EDA knows, Denali threw a party at every DAC for what seems like forever…

• 3 min read
dac2016 , DAC , Denali Party , disco inferno , Denali , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays—Modular VIP Architecture

In this week's Whiteboard Wednesdays video, Liron Stoler describes how the Cadence…

• less than a min read
Verification IP , Whiteboard Wednesdays , IP , VIP , system-level verification , block-level verification , modular architecture

Breakfast Bytes

CDNLive EMEA: Memories Are Made of This

At CDNLive in Munich, Amjad Qureshi talked about High-Speed DDR and LPDDR Memory…

• 4 min read
LPDDR , CDNLive EMEA , memory IP , DDR , memory interface IP

RF Engineering

Cadence Presenting Four Spectre RF MicroApp Papers at IMS2016, May 22-27

Hello Spectre RF Users, Next week is my all time favorite technical conference -…

• less than a min read
RF , RF Simulation , wireless , analog/RF , HBnoise , Circuit simulation , Wilsey , HB , Spectre RF , pnoise , phase noise , Schaldenbrand , spectreRF , RF design , harmonic balance , pss

Breakfast Bytes

EDPS Cyber Security Workshop: "Anything Beats Attacking the Crypto Directly"

Many of the security breaches that you read about are the results of software failures…

• 5 min read
security , fault injection , side channel attack , Monterey , differential power analysis , EDPS , riscure , cyber security , Breakfast Bytes

Breakfast Bytes

Can You Trust Your IoT Supplier?

A few weeks ago, Nest announced that it was shutting down Revolv. You probably don…

• 4 min read
alphabet , IoT , revolv , tesla , Internet of Things , nest , Breakfast Bytes

Breakfast Bytes

CDNLive EMEA: Do You Know What a FIT Is?

ADAS changes everything about automotive and requires a whole new range of skills…

• 6 min read
functional safety , CDNLive EMEA , automotive design , FIT

Breakfast Bytes

Cadence at DAC: Experts, Presentations, Lunches...and Denali Party Instructions

Cadence is doing a lot at DAC as usual. Here is a summary. But read it carefully…

• 4 min read
dac2016 , DAC , expert bar , Austin , Denali Party , dac53 , Lip-Bu Tan , Denali , 53dc , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays—Tensilica Vision P6 DSP Enhanced for CNN

In this week's Whiteboard Wednesdays video, Dennis Crespo discusses the significant…

• less than a min read
DSP , Whiteboard Wednesdays , IP , Vision P6 , Tensilica , convolutional neural networks , CNN

Breakfast Bytes

Bayern München Come to CDNLive EMEA

CDNLive EMEA is nominally held in Munich (München in German) but, in fact, is held…

• 5 min read
Munich , CDNLive , CDNLive EMEA , Breakfast Bytes , Bayern München
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