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Digital Design: Library Characterization Tidbits: The Perfect Solution for Validating Libraries

HelenShi

A library view contains electrical information that is used throughout design implementation starting from logic synthesis through design optimization to the final signoff verification.
- 11 Sep 2020
Breakfast Bytes: Use Your Imagination to Get Smaller, Faster Chips

Paul McLellan

At the recent CadenceLIVE Americas, Nick Loebner of Imagination Technologies presented Delivering Best PPA on PowerVR GPUs Using Genus/Innovus Digital Implementation System. You probably already know that Imagination Technologies license GPU IP....
- 11 Sep 2020
カスタムIC／ミックスシグナル: Virtuoso Video Diary: 信頼性解析の改善

Custom IC Japan

IC6.1.8/ICADVM18.1 ISR3のVirtuoso® ADE Assembler および Virtuoso ADE Explorer で、信頼性解析の実行方法を完全に変更する、改良されたReliability Options フォームを導入しました。これまで以上に物事をより良くするために、ケイデンスは信頼性解析の改良を続けています。このブログでは、すでに持っているものを再利用するという概念を中心とした2つの機能強化について説明します。ストレス・ファイルの再利用信頼性解...
- 10 Sep 2020
Analog/Custom Design: Virtuosity: Examining Post-Layout Capacitance Using Virtuoso ADE Assembler and ADE Explorer

Arja H

Post-Layout has become a hot topic recently. This has kept me and several other engineers very busy for the past year or so. One of the new, and exciting post-layout features that we have added to Virtuoso ADE Assembler and Virtuoso ADE Explorer is the ability to view the Spectre Classic Simulator netcap report.
- 10 Sep 2020
Breakfast Bytes: HOT CHIPS: The Space Race for the Biggest ML Machine

Paul McLellan

At the recent HOT CHIPS, the Sunday morning tutorial was on scale out of deep learning training. I covered the introduction in my post HOT CHIPS: Scaling out Deep Learning Training. The second half of the morning was devoted to some of the biggest sc...
- 10 Sep 2020
Verification: Mellanox's Tips and Tricks for Maximizing Your Palladium Unit

XTeam

Looking to learn more about the best practices for emulating today’s billion-gate-plus designs? Rest assured—we’ve got you covered.

Cadence has been partnered with Nvidia Mellanox for years, helping them build complete end-to-end solutions for everything from networking to data centers. Mellanox provides and handles every aspect of the process, and they’ve got a long track record of delivering breakthrough…
- 9 Sep 2020
Breakfast Bytes: OIP Ecosystem Forum 2020

Paul McLellan

Last Tuesday was the virtual TSMC OIP Ecosystem Forum. Apart from being virtual, the format was similar to the usual. Cliff Hou, Senior Vice President of Technology Development, opened the day with a summary of where everything is in the ecosyst...
- 9 Sep 2020
System, PCB, & Package Design : BoardSurfers: Find by Name or Find by Query - That is the Question!

BarbS

You must be using find utility day in and day out, but if you are unfamiliar with Find by Query in Allegro Layout Editors, read on. Layout editors retained the original Find by Name when developing a new utility to do what Find by Name cou...
- 8 Sep 2020
System, PCB, & Package Design : IC Packagers: Preparing a Completed Package for Mounting on a PCB

Tyler

We’ve covered all the different types of die components and how they interface with the package substrate coming into Allegro Package Designer. But, the package component (whether it’s a BGA, LGA, lead frame, or something else) is destine...
- 8 Sep 2020
Breakfast Bytes: Andrew Kahng and Matthew Morrison on Industry and Academia

Paul McLellan

I attended two presentations on the academic track at the recent CadenceLIVE Americas. The first was Andrew Kahng's presentation A 'Life Cycle' of Teaching and Research on EDA and IC Implementation Methodology. The second was Matthew...
- 8 Sep 2020
定制IC芯片设计 : Virtuoso Meets Maxwell: 当裸片版图没有Bump，有Pad Shapes时，怎么输出裸片版图?

deeptig

如果您的裸片版图不是通过Bumps，而是通过 pad shapes和标签来识别I / O位置，那么您可能会有种无所适从的感觉。因此在这篇文章中，我将为大家介绍一种新的适用于裸片版图的解决方案。
- 7 Sep 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Thinking Outside the Chip--Advantages of Interoperability Between Best-In-Class IC and IC Packaging Design and Verification Tools

danbaldwin

Many of today’s analog, RF, and mixed-signal designs require the integration of multiple ICs across varying substrate technologies to achieve required performance goals. The integration of heterogeneous devices allows designers to achieve results that can’t easily be duplicated using a monolithic IC (SoC) design approach. At the same time, heterogeneous integration introduces a whole new set of challenges for today’s…
- 7 Sep 2020
Breakfast Bytes: Sunday Brunch Video for 6th September 2020

Paul McLellan

https://youtu.be/bj1-b3YpuXg Made in "Costa Rica" Monday: Cadence Wins Texas Instruments' Supplier Excellence Award Tuesday: InspectAR: Augmented Reality in Newfoundland Wednesday: CadenceLIVE India 2020 Preview Thursday:&nbsp...
- 6 Sep 2020
カスタムIC／ミックスシグナル: Virtuosity: 日本の読者に朗報です

Custom IC Japan

最近私たちは、ノートパソコン、スマートフォン、テレビなど、画面の前でほとんどの時間を費やしています。これらのガジェットは、自宅やオンライン・プロジェクト、その他の仕事関連のタスクでの作業を簡単にサポートする、最高の仲間になりました。そして、私たちが余暇に視聴するために利用できる多くの驚くべき魅力的なコンテンツがあることを忘れないで下さい。問題は、テレビ番組で家族のそれぞれの好みが異なるときに発生します。しかし、最近、みんなの注目を集めているという共通のコンテンツが1つあります。...
- 3 Sep 2020
Breakfast Bytes: Labor Day Offtopic: Microroasting Coffee

Paul McLellan

Labor Day is coming up on Monday. Friday is also a Cadence holiday and Breakfast Bytes will not appear. So today is the last post before a holiday, and as always I write about something non-electronic. Today, coffee. Microroasting sounds like somethi...
- 3 Sep 2020
PCB設計／ICパッケージ設計: inspectAR: ニューファンドランドの”拡張現実”（AR）

SPB Japan

先日、CadenceLIVEでのAnirudhの基調講演についてAnirudh's Keynote: A New Product...and an Acquisition で取り上げました。この中でinspectARの買収について言及がありました。もっと詳しい話を聞くため、私はCEOのMihir Shahにコンタクトを取りました。最初の驚きは、同社がカナダのニューファンドランドを拠点としていることです。インド同様に、ニューファンドランドも1時間単位ではないタイムゾーンを採用する地域の1...
- 2 Sep 2020
System, PCB, & Package Design : BoardSurfers: Implementing SKILL Code

Rachna2018

This post is in continuation of Extending Allegro Layout Capabilities with SKILL, where I described how SKILL code can make things faster and more efficient even without having to code from scratch. In this post, we’ll see sample implementations...
- 2 Sep 2020
Breakfast Bytes: CadenceLIVE India 2020 Preview

Paul McLellan

In a normal year, I would already have my plane ticket to fly to Bangalore for CadenceLIVE India. It's an insane trip, in some ways, with about 40 hours of travel to attend about 16 hours of the actual event spread over two days. Of course, ...
- 2 Sep 2020
Verification: Xcelium ML: The Next Big Thing in Regression

XTeam

Looking for that extra kick in your regression performance? Cadence’s Xcelium Logic Simulator has a new feature just for you. Harnessing the power of machine learning, which is one of the areas of computational software innovation, Xcelium ML is here to help you optimize your regressions.

The inherently iterative, data-driven nature of simulation seems ripe for a machine-learning assisted tool, and Xcelium ML is here to fill…
- 1 Sep 2020
System, PCB, & Package Design : IC Packagers: How Die Stacking Works in Allegro Package Designer

Tyler

Recently, we’ve covered some basics about why imported dies default to chip-down flip-chips and even the different types of mirroring. To close on the topic of dies, die stacks, and the interaction of components why may interface together witho...
- 1 Sep 2020
Breakfast Bytes: InspectAR: Augmented Reality in Newfoundland

Paul McLellan

I covered Anirudh's CadenceLIVE keynote in my post Anirudh's Keynote: A New Product...and an Acquisition. The acquisition mentioned was InspectAR. I contacted Mihir Shah, the CEO, to find out more. The first surprise is that the company is based in N...
- 1 Sep 2020
PCB設計／ICパッケージ設計: TSMC: スペシャルティープロセスとスペシャルティーパッケージング

SPB Japan

先週の月曜日に、TSMC Technology Summit 2020がありました。もちろん、バーチャルでの開催です。それについては、別稿のTSMC Technology Symposium: All the Processes, All the Fabs(*英語)で取り上げました。今回の記事はスペシャルティープロセスとアドバンスドパッケージについてで、これはTSMCでは3DFabricという名称が使われているものです。スペシャルティーテクノロジー Kevin Zhangがスペシャルティー...
- 31 Aug 2020
Digital Design: Voltus Voice: Tempus Power Integrity Solution - Find Those Needles in the Haystack Quickly!

Jerry Zhao

This blog introduces the Tempus Power Integrity Solution that integrates the Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution signoff engines to find silicon performance failures missed with traditional IR analysis.
- 31 Aug 2020
Digital Design: Use the Industry’s Leading Digital Implementation Flow from inside Virtuoso with a Package Sized and Priced Perfect for Your Next Mixed Signal Project!

MJ Cad

Hi Everyone, Does the idea of using the best digital implementation tools on the market for your block sound interesting to you, but the full capacity is overkill, setup too daunting, or costs too high? If the answer is yes, do not worry; Cadence has...
- 31 Aug 2020
Verification: The Best Way to Learn SystemVerilog Accelerated Verification with UVM – Blended Training

SAIKAT SANA

UVM is a heavily used, standard, proven, easy-to-use, automated verification methodology in our current industry. With the growing use of UVM methodology, engineers need to have an in-depth knowledge. For someone getting started with UVM, it can be challenging and a steep learning curve. So, we offer a comprehensive and adaptable course SystemVerilog Accelerated Verification with UVM to sharpen your UVM skills.

This course…
- 31 Aug 2020

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