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While on a long drive, I like to sing along; say Eye of the Tiger or Johny B Goode or Sweet Home Alabama (even though I don’t live in Alabama), the music being an active part of the journey, especially when I am just beginning the drive, fresh and eager, looking forward to the trekking and wildlife sightings.  Compare this with the schematic design phase. Whistling and nodding while placing the parts: here’s the…

Cutting-edge innovation…Top-down planning…Reliable and formalized verification…Scalable performance!
These are the current buzzwords floating around in the electronic design automation industry. In fact, these buzzwords and more describe the new release of Virtuoso^® ADE Verifier in IC6.1.8 and ICADVM18.1. Analog verification methodology is ever-changing. With the introduction of very large and…

Recently, Bosch Sensortec has been using Specman for their functional verification needs in their Inertial Measurement Unit, and they’re loving it.

Why is Specman so cool? Well, it’s implementing the familiar UVM in e, which provides the tools and infrastructure to easily build extendable, maintainable, and reusable verification components. If you use Specman, you’ll see big productivity increases. For a lot of…

If you’re leaving 2018 with the feeling that your SystemVerilog skills are lacking, don’t worry—there’s a new series of Cadence Training Bytes to help you hit the ground running in 2019. Here you’ll find eight new YouTube videos all about SystemVerilog classes.

You can find the first video here.

Here’s a quick table of contents:

SystemVerilog Classes 1: Basics

This video goes over the…