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Latest Blog Posts

  • The Future Is Here: Physical AI Takes the Stage at SXSW 2025

    Corporate News: The Future Is Here: Physical AI Takes the Stage at SXSW 2025

    Corporate
    Corporate
    Artificial intelligence has advanced by leaps and bounds in recent years, transforming how we gather and utilize knowledge. 2025 is marking the dawn of a new era—the rise of physical AI. If you've noticed humanoid robots, self-driving cars, an...
    • 18 Feb 2025
  • Cadence Recognized for Accelerating AI and 3D-IC Applications by Samsung Foundry

    Corporate News: Cadence Recognized for Accelerating AI and 3D-IC Applications by Samsung Foundry

    Corporate
    Corporate
    Cadence and Samsung Foundry work with some of the leading semiconductor companies in the world. Together, they work to develop design solutions for next-generation AI and 3D-IC applications. Cadence and Samsung Foundry collaborate to innovate technol...
    • 17 Feb 2025
  • AI's Rapid Growth: The Crucial Role of High Bandwidth Memory

    SoC and IP: AI's Rapid Growth: The Crucial Role of High Bandwidth Memory

    Subash Peddu
    Subash Peddu

    System efficiency is dictated by the performance of crucial components. For AI hardware systems, memory subsystem performance is the single most crucial component. In this blog post, we will provide an overview of the AI model landscape and the impact of HBM memory subsystems on effective system performance.

    AI models have grown from a few billions of parameters from the early 90s to today’s Trillion Parameter Models…

    • 16 Feb 2025
  • BoardSurfers: PCB Editor - Topology Workbenchフローによる設計最適化

    PCB解析/ICパッケージ解析: BoardSurfers: PCB Editor - Topology Workbenchフローによる設計最適化

    SPB Japan
    SPB Japan
    PCB設計者は、信号解析チームまたは整合性チームと連携して配線前または配線後の解析を実行し、その結果に基づいて設計制約、フロアプラン、またはトポロジを変更する必要があります。Allegro PCB EditorとSigrity Topology Workbenchアプリケーションは、シームレスな統合を提供し、繰り返しの再設計の時間を節約するのに役立ちます。  PCB Editorは、プロジェクトの作成、ライブラリの管理、回路図エディタ、パッケージング、コンポーネントの配置と配線、および...
    • 12 Feb 2025
  • 米Broadcom社がSpectre FMCをタイミングばらつき解析に活用

    カスタムIC/ミックスシグナル: 米Broadcom社がSpectre FMCをタイミングばらつき解析に活用

    Custom IC Japan
    Custom IC Japan
    Broadcomは、CadenceのSpectre FMC解析とSpectreシミュレーションのマルチプロセッサモードを用いることで、精度を損なうことなくモンテカルロ解析時間の短縮を達成できました。このブログでは、Spectre FMCを使用してBroadcomが達成した精度と性能の向上について説明します。
    • 12 Feb 2025
  • Voltus IC Power Integrityを使用して3D-IC 設計の課題を克服

    PCB解析/ICパッケージ解析: Voltus IC Power Integrityを使用して3D-IC 設計の課題を克服

    SPB Japan
    SPB Japan
    3D-ICの電源ネットワーク設計と解析は、複雑で大規模な電源ネットワークのため、大きな課題となっています。さらに設計者は、インターポーザ、複数のダイ、シリコン貫通ビア(TSV)、誘電体貫通ビア (TDV) を介した電源配線の複雑さに対処する必要があります。 CadenceのIntegrity 3D-ICプラットフォームとVoltus IC Power Integrityソリューションは、3D-IC電源ネットワークの初期検証や3D-ICチップ中心および階層的手法によるパワーインテグリティ (PI)...
    • 12 Feb 2025
  • Addressing Sequential Elements Optimization in the VLSI Chip Design

    Digital Design: Addressing Sequential Elements Optimization in the VLSI Chip Design

    Neha Joshi
    Neha Joshi

    With highly advanced technology, the real designs are getting complex, making the design optimization process complicated and comprising the design results. The sequential cells play a vital role in the chip's optimization and functioning.

    Constant, merged, and unused flops, among other factors, impact the chip design's power, performance, and area (PPA) during the synthesis stage. Is there any way to handle the flops…

    • 12 Feb 2025
  • Software-defined vehicle and Cadence

    Corporate News: Driving the Future of Mobility with Cadence

    Vinod Khera
    Vinod Khera
    Back in November 2024 Cadence kicked-off a CadenceTECHTALK webinar series called “The Road Ahead: Navigating Trends and Tools in Automotive Design with Cadence”. In 10 webinars, Cadence experts discuss the rapidly evolving automotive land...
    • 12 Feb 2025
  • Knowledge Booster Training Bytes: Simplifying Shapes in the Virtuoso EM Solver

    Analog/Custom Design: Knowledge Booster Training Bytes: Simplifying Shapes in the Virtuoso EM Solver

    Pratul Nijhawan
    Pratul Nijhawan

    In this Knowledge Booster blog, let us discuss an important feature of the Virtuoso electromagnetic (EM) solver integration for performing EM simulations with the EMX Solver (in Electromagnetic Solver Assistant): Shape Simplification. By simplifying the shapes of EM models, the number of unknowns is reduced, simplifying the overall model. This leads to faster EM simulations of the IC structures.

     In the Electromagnetic…

    • 11 Feb 2025
  • Unlock Deeper Flow Insights with the V2-f Turbulence Model

    Computational Fluid Dynamics: Unlock Deeper Flow Insights with the V2-f Turbulence Model

    Gaurav
    Gaurav
    Key Takeaways A ‘code-friendly’ variant of the model is proposed to enhance numerical stability. It has proven advantageous if an implicit segregated equation-by-equation approach is used. This modification alleviates the ‘stiffnes...
    • 11 Feb 2025
  • 今、お困りの設計課題の解決ヒントに!ケイデンス製品ユーザー事例の資料をダウンロード頂けます

    カスタムIC/ミックスシグナル: 今、お困りの設計課題の解決ヒントに!ケイデンス製品ユーザー事例の資料をダウンロード頂けます

    Custom IC Japan
    Custom IC Japan
    昨年実施したCadenceCONNECTイベントでのご講演資料のご案内です。ケイデンス製品ユーザーによるICおよびSystem設計の課題に対する解決事例を掲載しましたので、是非ご覧下さい。
    • 11 Feb 2025
  • Sigrity and Systems Analysis 2024.1 新機能ハイライト

    PCB解析/ICパッケージ解析: Sigrity and Systems Analysis 2024.1 新機能ハイライト

    SPB Japan
    SPB Japan
    Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2024.1リリースが Cadence Downloads. サイトからダウンロード可能となりました。このリリースで改修された項目は、インストールに含まれているREADME.txtをご参照ください。 SIGRITY/SYSANLS 2024.1 ここにSIGRITY/SYSANLS 2024.1リリースの主要なアップデート内容をいくつかリストしました。このリリースに含まれる全ての新機能・改善機能...
    • 11 Feb 2025
  • Experience Cadence Innovations at NVIDIA GTC 2025

    Corporate News: Experience Cadence Innovations at NVIDIA GTC 2025

    Corporate
    Corporate
    NVIDIA GTC 2025 offers a pivotal opportunity for engineers and decision-makers shaping the future of electronics, systems, and data centers. For those leveraging Cadence tools, this event offers not only insights into cutting-edge technology but also...
    • 11 Feb 2025
  • Intelligent Custom Signoff Closure with the Quantus Insight Solution

    Analog/Custom Design: Intelligent Custom Signoff Closure with the Quantus Insight Solution

    Justas Lukosiunas
    Justas Lukosiunas

    Running inside the Virtuoso Platform, the Quantus Insight Solution offers unique capabilities to analyse and mitigate layout parasitics in custom layout design. Particularly at advanced nodes, interconnect RCs can strongly affect design performance and power.

    Engineered for handling large DSPF files, the Quantus Insight Solution offers a comprehensive array of analyses featuring rapid root cause identification, a what…

    • 11 Feb 2025
  • Training Insights – Electromagnetic Simulations Using the EMX Solver

    Analog/Custom Design: Training Insights – Electromagnetic Simulations Using the EMX Solver

    Sanjeev Kumar
    Sanjeev Kumar

    This one-day training course is an in-depth training on EMX Solver, a large-scale, full-wave, planar 3D electromagnetic simulator for designing and verifying Integrated Circuits (ICs). The EMX simulator is a powerful engine that simulates electromagnetic (EM) effects in circuits in a unified manner.

    The course is characterized as follows:

    • This course will start by defining the EM Simulator, explaining basic EM Theory…
    • 10 Feb 2025
  • The Year That Was: PCB and Package Design Training, Blogs, and Videos in 2024

    System, PCB, & Package Design : The Year That Was: PCB and Package Design Training, Blogs, and Videos in 2024

    ulrike
    ulrike
    Happy New Year! As another year has started, it’s time to reflect on our top blogs, training sessions, and training highlights from the last year and recap the significant news that emerged. Over the past year, we published 21 training blogs fo...
    • 10 Feb 2025
  • Cadence業界首款Arm架構系統Chiplet問世

    Spotlight Taiwan: Cadence業界首款Arm架構系統Chiplet問世

    candyyu
    candyyu
    本文翻譯自Cadence Community Blogs原文: Cadence Unveils Arm-Based System Chiplet Cadence宣佈了突破性的成就:業界首款以Arm架構為基礎的系統級小晶片(Chiplet)完成開發並成功投片;這個創新成果標誌了Chiplet技術的關鍵性進展,也是Cadence致力於透過其Chiplet結構與框架推動領先業界解決方案的承諾兌現。 業界首款系統Chiplet Cadence取得的重大進展,是成功完成業界第一款系統級Chiplet的原型...
    • 7 Feb 2025
  • Cadence與台積電聯手塑造3D-IC的未來

    Spotlight Taiwan: Cadence與台積電聯手塑造3D-IC的未來

    candyyu
    candyyu
    本文翻譯自Cadence Community Blogs原文: Cadence Collaborates with TSMC to Shape the Future of 3D-IC快速演進的人工智慧(AI)已經成為今日半導體產業主要推動力,隨著AI驅動的運算與記憶體密集應用需求持續增加,傳統的單晶片設計已經難以跟上。為因應以上問題,小晶片(Chiplet)與3D-IC等創新方法正在重塑晶片設計領域,而Cadence與台積電(TSMC)處於這場革命的最前線,也正在攜手合作為先進製程節點晶片與3D...
    • 7 Feb 2025
  • Skycore Partners with Cadence to Create Energy-Efficient Data Center ICs

    Corporate News: Skycore Partners with Cadence to Create Energy-Efficient Data Center ICs

    Corporate
    Corporate
    The explosive surge of artificial intelligence and electrification is driving a sharp increase in energy consumption within data centers. U.S. data center power demand is expected to rise from 147TWh in 2023 to 606TWh by 2030, accounting for 11.7% o...
    • 6 Feb 2025
  • Free Signal Integrity

    System, PCB, & Package Design : Free Signal Integrity

    MSATeam
    MSATeam

    CMP-70What do we mean by free signal integrity? Be sure to attend our joint Wild River Technology/Cadence DesignCon 2025 technical session, where we will unveil how understanding anisotropic materials and tolerances in the design of PCBs can increase performance at 112/224Gpbs and beyond. The talk will take place on Wednesday, January 29, 11:15am – 12:00pm in Ballroom B.

    Uncertainty in as-fabricated (AF) dimensions and…

    • 5 Feb 2025
  • Symmetric Multiprocessing (SMP) RTOS on Xtensa Multicore

    SoC and IP: Symmetric Multiprocessing (SMP) RTOS on Xtensa Multicore

    Nayan Gaywala
    Nayan Gaywala

    An increasing number of multi-threaded embedded applications want to leverage multicore designs. Symmetric Multiprocessing (SMP) RTOS provides automatic load balancing of multiple threads in a multicore environment. Also, numerous legacy multi-threaded embedded applications are deployed on a single-core RTOS that customers want to move to a multicore environment. For these reasons, application developers often need an…

    • 29 Jan 2025
  • The Year That Was: Knowledge Booster Training Bytes Blog and Video Highlights from 2024

    Analog/Custom Design: The Year That Was: Knowledge Booster Training Bytes Blog and Video Highlights from 2024

    Parula
    Parula
    This blog takes us back into 2024 and highlights our new blogs, trainings and training bytes throughout the year. It also mention the new created digital badges and the trainings that were updated to the next version and amongst others our “Accelerated Learning” training option.
    • 29 Jan 2025
  • Virtuoso Studio IC23.1 ISR12 Now Available

    Analog/Custom Design: Virtuoso Studio IC23.1 ISR12 Now Available

    Virtuoso Release Team
    Virtuoso Release Team
    Virtuoso Studio IC23.1 ISR12 production release is now available for download.
    • 29 Jan 2025
  • Need to Reconfigure Your SoC to Meet Functional Safety Standards?

    Digital Design: Need to Reconfigure Your SoC to Meet Functional Safety Standards?

    FormerMember
    FormerMember

    The ISO 26262 standard provides functional safety guidance for semiconductors used in the automotive industry based on the foundational IEC 61508 standard. The Cadence Midas Safety Platform exchanges safety-related information across Cadence tools for a detailed safety analysis and generates a configuration database for your design. The semiconductor vendor does the safety analysis of the fully featured SoC and creates…

    • 28 Jan 2025
  • Cadence Ireland Sponsors Fahy Rovers Girls Soccer Team

    Life at Cadence: Cadence Ireland Sponsors Fahy Rovers Girls Soccer Team

    Suzanne Cawley
    Suzanne Cawley
    Recently, Cadence Ireland sponsored training tops for a local girls' soccer team, Fahy Rovers. Read on to learn more about how the sponsorship idea came about and why this team deserved it!
    • 28 Jan 2025
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