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Digital Design: Relax in Summer with Cooler IC chips and Ice-Cream! Do you want to Explore the Recipe?

Neha Joshi

Are you passionate about cooking? Err... Don't think it is a regular cooking class.

Here we tend to cook cooler power solutions!

Do you know creating a cooler IC chip is as easy as enjoying the ice-cream in summer to beat the heat?

Low-Power synthesis is one of the important stages in the full IC flow. Using various techniques, you synthesize the design from behavioral description to gates while optimizing for dynamic…
- 12 Oct 2022
Breakfast Bytes: TSMC OIP Preview 2022

Paul McLellan

I have pointed out before that you really only get two opportunities a year to get briefed on TSMC's roadmap. One of those is OIP, technically the Open Innovation Platform Ecosystem Forum. This year it is going to be in-person at the Santa Clara ...
- 12 Oct 2022
Breakfast Bytes: Cadence Certus Closure Solution: Automated Full-Chip Optimization

Paul McLellan

Today, we announced the Cadence Certus Closure Solution, the first-of-its-kind fully automated environment featuring massively parallel and distributed architecture. It supports design optimization and signoff with unlimited capacity deliv...
- 11 Oct 2022
Life at Cadence: Artificial Intelligence Is Revolutionizing Computational Software

Corporate

What does the term computational software mean? The shortest explanation is that computational software is computer science plus math. That is what is at the core of Cadence technology, and what the engineering tools industry has been creating since...
- 11 Oct 2022
Computational Fluid Dynamics: Last Week at Fidelity CFD

John Chawner

Rise and shine for another week in the world of CFD. Here's what you missed last week from us here at Cadence Fidelity CFD. (Let's go back two weeks because there wasn't a post last Monday.) From the Blogs On-Demand Webinar—Modeling...
- 10 Oct 2022
Breakfast Bytes: 3D Heterogeneous Integration (3DHI)

Paul McLellan

Shakespeare (in Romeo and Juliet) wrote: What's in a name? That which we call a rose by any other name would smell just as sweet. The Implication is that names do not matter. Shakespeare was clearly not in marketing, where names are acknowledge...
- 10 Oct 2022
Academic Network: Academic and Entrepreneur Tracks at CadenceLIVE Europe 2022

Anton Klotz

I am very happy to announce that registration for the in-person CadenceLIVE Europe user conference has opened! The conference will be hosted in Munich at a new venue, the Hilton Park Hotel. The Cadence Academic Network is turning 15 this year,...
- 10 Oct 2022
Verification: USB4 Version 2.0 Announced

Neelabh

USB Promoter Group has announced the pending release of the USB4® Version 2.0 specification, which will enable up to 80 Gbps operation over the USB Type-C® cable and connector.

As per this announcement, the key characteristics of the updated USB4 solution include:

• Up to 80 Gbps operation, based on a new physical layer architecture, using existing 40 Gbps USB Type-C passive cables and newly-defined 80 Gbps USB…
- 10 Oct 2022
Computational Fluid Dynamics: Generate Quads/Hexes at the Speed of Trias

Veena Parthan

The quadrilateral-dominant meshing algorithm within Fidelity Pointwise generates surface meshes consisting of well-aligned quadrilateral cells, and it does so with the same speed as it takes for generating all triangular meshes.
- 10 Oct 2022
Breakfast Bytes: Tesla AI Day 2022

Paul McLellan

On Friday, September 30th, from 6 pm until well after 9 pm Tesla held its AI Day 2022. Working for three hours is not the best way to start the weekend, but that's what I found myself doing. Luckily, the whole evening was fascinating. I...
- 7 Oct 2022
Verification: Struggling with Coverage Convergence – Give your Verification Wings with Xcelium Machine Learning App

Anika Sunda

Functional verification consumes more than 70% of the labor invested in today’s SoC designs. Yet, even with such a large investment in verification, there’s more risk of functional failure at tape out than ever before. The primary reason is that the design team does not know where they are, in terms of functional correctness, relative to the tape-out goal. Coverage Closure in SoC verification is like chasing a mirage…
- 6 Oct 2022
PCB設計／ICパッケージ設計: APD Plus を日本語で自習してみませんか？

SPB Japan

Cadence Response Center (CRC)のホームページには、”ラーニング”というメニューがあり、製品の操作法や活用法を学習していただくのに便利な情報へのリンクが集められています。例えば、”オンラインコース”は、無償でご利用いただけるオンラインのトレーニングコースにアクセスできます。コロナ禍で対面式のトレーニングが難しくなっている今、ご自身のペースで進められるオンラインコースはお勧めしたいアイテムの一つです。あるいは、&rdqu...
- 6 Oct 2022
Life at Cadence: NVIDIA Embraces the Groundbreaking Technology, Dynamic Duo 2.0

Corporate

When it comes to accelerated computing, NVIDIA is an industry pioneer, particularly so in the field of AI technology. The tremendous amount of power that is required to tackle AI algorithms and workloads is inherent in NVIDIA’s graphical proce...
- 6 Oct 2022
Life at Cadence: Heterogeneous Integration Co-Design Won’t Be Easy – Here’s What You Need to Succeed

Tom Beckley

Heterogeneous integration is ushering in a new era of silicon chip design with collaboration at its core—one that lives or dies on how well your teams work together.
- 6 Oct 2022
Breakfast Bytes: There Is Not Enough Power

Paul McLellan

In almost every episode of Star Trek (the original series), Captain Kirk would have to call down to Scotty in the engine room and demand more power. Well, the hyperscaler datacenter companies are Captain Kirk, calling down to the electricity companie...
- 6 Oct 2022
Computational Fluid Dynamics: Wave Generation Revisited and Other Highlights of Fine Marine v11.1

AnneMarie CFD

The newest version of Fine Marine - Cadence's CFD software specifically designed for Marine Engineers and Naval Architects - is out now. Discover re-conceptualized wave generation, drastically expanding the range of waves and the accuracy of the modeling and advanced post-processing tools.
- 5 Oct 2022
Life at Cadence: Formula 1: Riding the Sustainability Wave to Full Electrification

Corporate

Understand the value of electrification when pushing the world towards sustainability
- 5 Oct 2022
Breakfast Bytes: Preview of Jasper User Group 2022

Paul McLellan

This year's Jasper User Group is coming up later this month on October 19th and 20th. Once again, we are back in person (I'll be there!) on the Cadence campus. There will also be a 3-hour webinar available before the event to provide an intro...
- 5 Oct 2022
Digital Design: Resolve Congestion and Physical Design Challenges Using Cadence Support and RAKs

Vinod Khera

Physical design challenges such as congestion, routing, on-chip variation (OCV), and unconstrained paths are significant issues in achieving the design goals. Managing the routing congestion and physical design challenges with the least amount of effort is a big problem for physical design engineers. Further, the usage of advanced nodes and increasing functionality over SoC is leading to rising complexity and conflicting…
- 4 Oct 2022
Data Center: Digital Twins: Six Steps to Address Data Center Thermal Challenges

Corporate

Data center digital twins address complex data center design challenges by virtualizing design and optimization
- 4 Oct 2022
Breakfast Bytes: The IBM 801, the RISC You've Never Heard of

Paul McLellan

In a recent post, RISC-V Tutorial, I wrote about the history of RISC-V. The "V" is the Roman numeral for five. Hence, this is pronounced "risk five." With a five in the name like that, the obvious question is, "What were RISCs 1 to 4?". In fact, ther...
- 4 Oct 2022
Breakfast Bytes: 30th Anniversary of Glengarry Glen Ross

Paul McLellan

Yesterday is the 30th anniversary of the release of the movie Glengarry Glen Ross. If you work in sales, you have almost certainly seen it. The movie was a critical success but didn't do well at the box office, probably because it is pretty depr...
- 3 Oct 2022
Computational Fluid Dynamics: 'Tweak' Your Grid! That's All It Needs

Veena Parthan

'Tweak' is a handy command that is part of your toolkit. It's not something you're likely to use every day, but it'll be there when you need it. It is a small feature that can make a major difference between a grid and a bunch of points on which you can't compute an accurate or converged CFD solution.
- 3 Oct 2022
RF Engineering: New Training Courses for RF/Microwave Designers Featuring Cadence AWR Software

Sherry Hess

Cadence AWR Design Environment Software Featured in Multiple Training Course Options: Live and Virtual Starting in October
- 2 Oct 2022
Breakfast Bytes: Sunday Brunch Video for 2nd October 2022

Paul McLellan

https://youtu.be/K4c92qNBoa0 Made on my balcony (camera Carey) Monday: CadenceLIVE Boston: The Current State of EDA Education Tuesday: RISC-V Tutorial Wednesday: Bluetoooth LE Audio, Hearing Aids, and Mindtree Thursday: When AI Rules the World, by Ha...
- 2 Oct 2022

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