Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Verification: Come Join Us for "Deep Dive into the UVM Register Layer" - A Webinar From Duolos

XTeam
Join us on September 14th for a free one-hour webinar on the finer aspects of the UVM register layer. We’ll be focusing on key aspects of the UVM Register Layer that can help you with your UVM modeling in ways you may not be aware of.

We’ll be covering the following topics:

How to use user-defined front doors and back doors to expand what the register layer can do

Understanding the role played by the predictor…
- 12 Sep 2018
Analog/Custom Design: Virtuoso: The Next Overture - Congestion Analysis with a New Perspective

Parula

Watch out for the exclusive set of routing features, along with the newly introduced Design Planner features in ICADVM 18.1, and then take a fresh new look at the new Congestion Analysis assistant.
- 12 Sep 2018
Breakfast Bytes: Spectre/Meltdown & What It Means for Future Design 2

Paul McLellan

I gave an introduction to speculative execution and the vulnerabilities that have come to light this year in yesterday's post Spectre/Meltdown & What It Means for Future Design 1. There were 4 panelists at Hot Chips, chaired by Partha Rangana...
- 12 Sep 2018
Breakfast Bytes: Spectre/Meltdown & What It Means for Future Design 1

Paul McLellan

At HOT CHIPS, one of the "keynotes" was actually a panel of what I'll call industry luminaries. They were discussing the implications of vulnerabilities such as Spectre, Meltdown, and the recently announced Foreshadow. This is the most ...
- 11 Sep 2018
Breakfast Bytes: CDNLive India

Paul McLellan

CDNLive India took place last week. As usual, I made the long trip from California, nearly 30 hours door to door. There is aways something remarkable on these long flights and this time it was the WiFi pricing. It is nearly 50% more ($30.00 vs $21.99...
- 10 Sep 2018
System, PCB, & Package Design : New Sigrity 3D Workbench Used in Designing and Optimizing Next Generation High-Speed Connectors

Sigrity

2018 is going to be remembered as the year of 3D for Sigrity. As part of Cadence’s Sigrity 2018 release, we introduced the new Sigrity 3D Workbench technology included as part of the Sigrity PowerSI® 3D EM Extraction Option...
- 8 Sep 2018
PCB、IC封装：设计与仿真分析: 升级到Allegro17.2-2016的10大理由之4：行业领先的背钻能力

TeamAllegro

背钻的发展历程 15年来，在很多电子设计中处理5Gbps或更高频率的高速接口布线已越来越常见。在信号过孔上存在Stub的情况下，高速信号换层将会对信号完整性产生巨大影响。总的来说，这些短截线会造成阻抗不连续和信号反射，严重影响有效数据传输速率的提升。（点击查看大图）如何消除电子短截线？使用一种称之为背钻的制板工艺，有时也被称为控制深度过孔。做好规化和控制，保证高速信号走在特定的布线层，以此来减小Stub的影响。用盲埋孔和微孔技术来布高速信号，这种方案可以解决一些局限和担忧，...
- 8 Sep 2018
PCB、IC封装：设计与仿真分析: 升级到Allegro17.2-2016的10大理由之3：新的PAD编辑器——不只是一个新GUI

TeamAllegro

客户反馈是产品改善的关键当您在理解Allegro 17.2-2016发行版的特点和优势时，我可以猜到您在想什么。“哦不，他们对我的工作环境做了什么破坏？”如果您已使用Allegro多年了，您就会理解我的意思。我们称之为零版本的发行版被用来建立数据库/改变架构，会导致某种程度上的升级中断。17.2有效结合了零版本和17.0 EAP(Early Access Program)版本内容，于是就有了17.2。多年前，当我们在考虑下一步需要开发什么时，我们首先就要从你们提交的客...
- 8 Sep 2018
RF Engineering: Measurement of Phase Noise in Oscillators

Jommy

The other day, I happened to sneak out some time for myself after having sent the kids to play in the neighborhood park. I made myself a hot cup of coffee and settled on the couch hoping to enjoy the silence in the house. But was it really ...
- 7 Sep 2018
Analog/Custom Design: Virtuoso: The Next Overture – Introducing Design Planner

Rishu Misri Jaggi

Watch out for our new layout design capability that allows you to plan more efficiently at the top level, block level, and at the cell level..
- 7 Sep 2018
Breakfast Bytes: PCAST: The President's Council of Advisors on Science and Technology

Paul McLellan

In January 2017, a report Ensuring Long-Term U.S.Leadership in Semiconductors was delivered to the President. It was not yet the 20th of the month, so that was still President Obama. I read the report at the time but made the mistake of not...
- 7 Sep 2018
Breakfast Bytes: What's For Breakfast? Video Preview September 10th to 14th 2018

Paul McLellan

https://youtu.be/iv9wdAVB6vg Coming from CDNLive India (camera Seena Shankar) Monday: CDNLive India Tuesday: Numbers Everyone Should Know Wednesday: Spectre/Meltdown and What It Means for Future Design 1 Thursday: Spectre/Meltdown...
- 6 Sep 2018
Breakfast Bytes: Numbers Everyone Should Know

Paul McLellan

At the recent HOT CHIPS, Paul Turner of Google Project Zero talked about numbers everyone should know. These numbers, actually latencies, seem originally to come from Peter Norvig but have been updated by a number of people since his original table, ...
- 6 Sep 2018
Breakfast Bytes: GLOBALFOUNDRIES Drops 7nm to Focus on Other Geometries

Paul McLellan

GF put out a press release last week with the title GF Reshapes Technology Portfolio to Intensify Focus on Growing Demand for Differentiated Offerings. What this actually means is that GF is putting its 7nm process development on hold ...
- 5 Sep 2018
Academic Network: APAC IC Design Contests

Tracy Zhu

China Graduate IC Design Contest Contest Duration: April – August 2018 This is Cadence’s second time supporting the China Graduate IC Design Contest. This contest provided graduate students with the opportunity to develop creative electro...
- 5 Sep 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - What You need to Know About ISO26262-2018 2nd Edition

References4U

In this week's Whiteboard Wednesdays video, the first in a multi-part series, Scott Jacobson explores the changes in the upcoming ISO26262-2018 standard update and how they affect semiconductor design.

https://youtu.be/QFV3KIUwJxs
- 4 Sep 2018
PCB、IC封装：设计与仿真分析: 升级到Allegro17.2-2016的10大理由之2：新的实时并行团队设计功能

TeamAllegro

利用团队设计实现快速设计无论如何，PCB团队设计总是实现快速设计的最佳捷径。您可以使用Allegro 17.2 2016版本中新的实时并行团队设计功能，通过动态分配资源来应对设计周期不断缩短的挑战。我们的产品给设计工程师提供一个快捷的方式，可分享共同的Allegro数据库，进行协同设计。无论是组建正规的设计团队或者是临时通知的任务，设计工程师仅需简单地分享他们当前的设计，并邀请其他设计师加入帮忙。您也可让专家做出贡献来加速项目进程。通过复制周围的数据库，剪切/粘贴设计更新到主数据库，无需增加设...
- 4 Sep 2018
Breakfast Bytes: Ambit Design Systems

Paul McLellan

Twenty years ago today, Cadence announced it was acquiring Ambit Design Systems. Actually, the anniversary of the announcement is really September 3rd, but since that is a public holiday this year, I slipped it a day. The actual acquisition didn'...
- 4 Sep 2018
Breakfast Bytes: Labor Day Off-Topic: Almost Everyone Has More Than the Average Number of Legs

Paul McLellan

It's Labor Day. Cadence is closed in the US. Unfortunately, I'm in India and it's not a holiday here. It's CDNLive India later in the week. As is traditional, I will post about...whatever I feel like. Everyone seems to like these off...
- 3 Sep 2018
Analog/Custom Design: Virtuosity: Opening Old ADE States and Views with ADE Explorer and ADE Assembler

Arja H

Have you found it a pain that when opening a Virtuoso ADE L state or a Virtuoso ADE XL view that the default application is still the old ADE L or XL? If you've moved on to Virtuoso ADE Assembler or Virtuoso ADE Explorer world then you need to change the application in the Open File dialog to ADE Explorer or ADE Assembler. To set the application by default we have added a couple of environment variables that you…
- 3 Sep 2018
Analog/Custom Design: Virtuoso IC6.1.7 ISR22 and ICADV12.3 ISR22 Now Available

Virtuoso Release Team

The IC6.1.7 ISR22 and ICADV12.3 ISR22 production releases are now available for download. To find out more, click here…
- 3 Sep 2018
PCB、IC封装：设计与仿真分析: 升级到Allegro17.2-2016的10大理由之1：先进的柔性和刚柔结合板设计支持

TeamAllegro

为何要刚柔结合？对几乎所有应用，客户一直希望能有更小、更轻、性价比更高的产品。竞争压力也促使设计工程师们以不断增长的速度将这些新产品带到市场。设计工程师们可使用柔性PCB材料（柔性/刚柔结合）来满足小型化需求、代替连接器，以提高产品性能。 (点击查看大图）有哪些新技术可支持刚柔结合设计？制造商对设计的进一步要求已准备好，如在柔性衬底上实现元件安装，支持多层柔性板以缩小尺寸，并提高高速性能。从第一次成功开始为了节省时间和成本，必须要尽早与制造商合作，来为您的刚柔结合PCB建立关于性能...
- 31 Aug 2018
Breakfast Bytes: HOT CHIPS Tutorial: On-Device Inference

Paul McLellan

The Sunday of the annual HOT CHIPS (the 30th!) conference is tutorial day. In the morning, it was the Blockchain, which I missed due to other commitments. in the afternoon it was Deep Learning. This was divided into 3 parts: Overview of Deep Learnin...
- 31 Aug 2018
Breakfast Bytes: Breakfast Buffet for August

Paul McLellan

https://youtu.be/elQgyXvkcjU The three highlighted posts for August were: Two posts on Shockley Labs: The Birthplace of Silicon Valley: 391 South San Antonio Road The Brief but Spectacular History of Shockley Labs SEMICON 5nm: 7nm Is Just a D...
- 30 Aug 2018
定制IC芯片设计 : Virtuoso: 新序曲—设计意图工具（Design Intent）工具简介

sarahfino

简化设计目标，并且给版图设计师们提供更多自由来实现他们的设计目标。
- 30 Aug 2018

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.