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System, PCB, & Package Design : System Analysis Knowledge Bytes: Simplifying Signal and Power Integrity Analysis with Sigrity Aurora

deeptik

This System Analysis Knowledge Bytes blog describes how Sigrity Aurora can help simplify signal and power integrity analysis. It gives an overview of all the workflows available in the Allegro In-Design (IDA) Environment including the new Interconnect Model Extraction workflow.
- 14 Oct 2022
Breakfast Bytes: Samsung Foundry Roadmap 2022

Paul McLellan

Recenty, it was the Samsung Foundry Forum (SFF). In fact, there was a pre-event for the press that morning (SFF started after lunch). I couldn't attend in person due to a personal conflict, but the press event was recorded and I received the slid...
- 14 Oct 2022
Computational Fluid Dynamics: Fidelity Pointwise 2022.1 Hot Fix 2 Now Available

AnneMarie CFD

Fidelity Pointwise 2022.1 Hot Fix 2 is now available for download and production use. Discover it's new features and download instructions.
- 14 Oct 2022
Academic Network: Shift-Left Methodology for the Development of Hardware Accelerators Education Kit Is Available Now

Anton Klotz

In order to describe the purpose of this education kit, let’s leave the EDA turf for a minute and enter the world of computer architecture. If you still remember the 80s, the PCs of that time had one single CPU (Central Processing Unit), which ...
- 13 Oct 2022
Life at Cadence: Hassle-Free Rigid-Flex PCB Bending EM Analysis

Ben Gu

The functionality, safety, and effectiveness of devices using rigid-flex PCBs are highly critical, especially for devices used in advanced medical implants, high-precision critical military equipment, and similar regulated and classified devices, mak...
- 13 Oct 2022
Life at Cadence: Butterfly Network Puts Ultrasound on a Chip with Cadence

Corporate

About two-thirds of the world’s population lacks access to medical imaging, whether in developing nations or in first-world countries with underserved communities. Butterfly Network, however, has a solution, and it’s built on a single chi...
- 13 Oct 2022
Breakfast Bytes: 2022 Kaufman Award Honors Giovanni De Micheli

Paul McLellan

This year's Kaufman Award honors Giovanni De Micheli, usually known as Nanni. Of course, with a name like that, you will guess correctly that he is Italian. However, despite being brought up in Italy, his career has spanned two main parts, neither of...
- 13 Oct 2022
Verification: Unraveling PCIe 6.0 FLIT Mode Challenges

xinmu

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer rate with PAM4 (Pulse Amplitude Modulation with 4 levels) modulation and uses FLIT (Flow Control Unit) as the unit of communication for efficiency. In ‘What Disruptive Changes to Expect from PCI Express Gen 6.0? we covered what significant features PCIe 6.0 evolved to embrace.

Amongst many new features and changes in PCIe 6.0…
- 12 Oct 2022
Analog/Custom Design: Virtuoso ICADVM20.1 ISR28 and IC6.1.8 ISR28 Now Available

Virtuoso Release Team

The ICADVM20.1 ISR28 and IC6.1.8 ISR28 production releases are now available for download.
- 12 Oct 2022
Verification: Importance of MDIO Interface for Ethernet.

AyushK

Media Independent Interface Management (MIIM), or Management Data Input/Output (MDIO), is a serial bus protocol and is used for the IEEE 802.3 Ethernet standard and Media Independent Interface (MII). The MIIM/MDIO protocol is a simple two-wire serial interface with specific terminology to define the various devices on the bus. The device driving the MDIO bus is identified as the Station Management Entity (STA). The STA…
- 12 Oct 2022
Life at Cadence: How Is the Semiconductor Industry Handling Scaling: Is Moore's Law Still Alive?

Vinod Khera

The chip design industry is going through exciting times. Process nodes with smaller geometries have always enticed chip manufacturers and OEMs, as it helps integrate more functionality over SoC. This reduction in the process nodes has been predicted...
- 12 Oct 2022
Digital Design: Relax in Summer with Cooler IC chips and Ice-Cream! Do you want to Explore the Recipe?

Neha Joshi

Are you passionate about cooking? Err... Don't think it is a regular cooking class.

Here we tend to cook cooler power solutions!

Do you know creating a cooler IC chip is as easy as enjoying the ice-cream in summer to beat the heat?

Low-Power synthesis is one of the important stages in the full IC flow. Using various techniques, you synthesize the design from behavioral description to gates while optimizing for dynamic…
- 12 Oct 2022
Breakfast Bytes: TSMC OIP Preview 2022

Paul McLellan

I have pointed out before that you really only get two opportunities a year to get briefed on TSMC's roadmap. One of those is OIP, technically the Open Innovation Platform Ecosystem Forum. This year it is going to be in-person at the Santa Clara ...
- 12 Oct 2022
Breakfast Bytes: Cadence Certus Closure Solution: Automated Full-Chip Optimization

Paul McLellan

Today, we announced the Cadence Certus Closure Solution, the first-of-its-kind fully automated environment featuring massively parallel and distributed architecture. It supports design optimization and signoff with unlimited capacity deliv...
- 11 Oct 2022
Life at Cadence: Artificial Intelligence Is Revolutionizing Computational Software

Corporate

What does the term computational software mean? The shortest explanation is that computational software is computer science plus math. That is what is at the core of Cadence technology, and what the engineering tools industry has been creating since...
- 11 Oct 2022
Computational Fluid Dynamics: Last Week at Fidelity CFD

John Chawner

Rise and shine for another week in the world of CFD. Here's what you missed last week from us here at Cadence Fidelity CFD. (Let's go back two weeks because there wasn't a post last Monday.) From the Blogs On-Demand Webinar—Modeling...
- 10 Oct 2022
Breakfast Bytes: 3D Heterogeneous Integration (3DHI)

Paul McLellan

Shakespeare (in Romeo and Juliet) wrote: What's in a name? That which we call a rose by any other name would smell just as sweet. The Implication is that names do not matter. Shakespeare was clearly not in marketing, where names are acknowledge...
- 10 Oct 2022
Academic Network: Academic and Entrepreneur Tracks at CadenceLIVE Europe 2022

Anton Klotz

I am very happy to announce that registration for the in-person CadenceLIVE Europe user conference has opened! The conference will be hosted in Munich at a new venue, the Hilton Park Hotel. The Cadence Academic Network is turning 15 this year,...
- 10 Oct 2022
Verification: USB4 Version 2.0 Announced

Neelabh

USB Promoter Group has announced the pending release of the USB4® Version 2.0 specification, which will enable up to 80 Gbps operation over the USB Type-C® cable and connector.

As per this announcement, the key characteristics of the updated USB4 solution include:

• Up to 80 Gbps operation, based on a new physical layer architecture, using existing 40 Gbps USB Type-C passive cables and newly-defined 80 Gbps USB…
- 10 Oct 2022
Computational Fluid Dynamics: Generate Quads/Hexes at the Speed of Trias

Veena Parthan

The quadrilateral-dominant meshing algorithm within Fidelity Pointwise generates surface meshes consisting of well-aligned quadrilateral cells, and it does so with the same speed as it takes for generating all triangular meshes.
- 10 Oct 2022
Breakfast Bytes: Tesla AI Day 2022

Paul McLellan

On Friday, September 30th, from 6 pm until well after 9 pm Tesla held its AI Day 2022. Working for three hours is not the best way to start the weekend, but that's what I found myself doing. Luckily, the whole evening was fascinating. I...
- 7 Oct 2022
Verification: Struggling with Coverage Convergence – Give your Verification Wings with Xcelium Machine Learning App

Anika Sunda

Functional verification consumes more than 70% of the labor invested in today’s SoC designs. Yet, even with such a large investment in verification, there’s more risk of functional failure at tape out than ever before. The primary reason is that the design team does not know where they are, in terms of functional correctness, relative to the tape-out goal. Coverage Closure in SoC verification is like chasing a mirage…
- 6 Oct 2022
PCB設計／ICパッケージ設計: APD Plus を日本語で自習してみませんか？

SPB Japan

Cadence Response Center (CRC)のホームページには、”ラーニング”というメニューがあり、製品の操作法や活用法を学習していただくのに便利な情報へのリンクが集められています。例えば、”オンラインコース”は、無償でご利用いただけるオンラインのトレーニングコースにアクセスできます。コロナ禍で対面式のトレーニングが難しくなっている今、ご自身のペースで進められるオンラインコースはお勧めしたいアイテムの一つです。あるいは、&rdqu...
- 6 Oct 2022
Life at Cadence: NVIDIA Embraces the Groundbreaking Technology, Dynamic Duo 2.0

Corporate

When it comes to accelerated computing, NVIDIA is an industry pioneer, particularly so in the field of AI technology. The tremendous amount of power that is required to tackle AI algorithms and workloads is inherent in NVIDIA’s graphical proce...
- 6 Oct 2022
Life at Cadence: Heterogeneous Integration Co-Design Won’t Be Easy – Here’s What You Need to Succeed

Tom Beckley

Heterogeneous integration is ushering in a new era of silicon chip design with collaboration at its core—one that lives or dies on how well your teams work together.
- 6 Oct 2022

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