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Latest Blog Posts

  • LPDDR5 Verification from PHY to System Level

    Verification: LPDDR5 Verification from PHY to System Level

    Vinod Khera
    Vinod Khera
    LPDDR5 DRAM aims to serve a wide array of markets and plays a vital role in the system’s performance. These performance expectations make the whole system verification extremely challenging and become more complex as the project evolves from IP Level verification to Memory sub-system and System-level as you start integrating the memory pieces in the whole SoC. In this blog, I will be discussing how Cadence helps to overcome…
    • 4 Apr 2022
  • Breakfast Bytes: Intelligent System Analog Design

    Paul McLellan
    Paul McLellan
    There are many perceptions about analog design that might have been true once. For example, all analog design is done by grey-haired designers with decades of experience wrestling the signals to the ground using just a polygon-based layout editor and...
    • 4 Apr 2022
  • PCB設計/ICパッケージ設計: BoardSurfers: Allegro PCB Editorでの寸法データ入力に関する概要

    SPB Japan
    SPB Japan
    プリント基板がより複雑かつ軽量になっていく中、費用対効果が高く信頼性の高い基板の設計・製造は、これまで以上に重要となっています。デザインの詳細情報が不正確/不完全では、アセンブリの工程で基板の製造に影響を与える可能性があります。PCBデザインに寸法データ(ディメンジョン)を追加することにより、そのPCBデータが製造用に出力されたときにすべてがぴったり合うようデザインに関する十分な詳細情報を提供できます。 なぜ寸法データが必要なのか? PCBに寸法データを付加する主な目的は、重要な穴の位置、PCB...
    • 3 Apr 2022
  • Combining Structured and Unstructured Meshes: The Holy Grail for CFD Engineers

    Computational Fluid Dynamics: Combining Structured and Unstructured Meshes: The Holy Grail for CFD Engineers

    AnneMarie CFD
    AnneMarie CFD
    Flow solvers must be able to read the type of meshes behind them, and as most flow solvers only accept either structured or unstructured meshes, this is can be a no-win situation. However, within Cadence's Omnis™︎ environment, users can switch between meshing approaches in a single click.
    • 1 Apr 2022
  • Breakfast Bytes: The All-Purpose EDA Keynote

    Paul McLellan
    Paul McLellan
    Today, it is April 1st and so it is tempting to do some spoof post, but most of those are lame. Plus, it is hard to surpass the BBC's 1957 news item about the spaghetti harvest. This fooled so many people since it was decades before the era when ...
    • 1 Apr 2022
  • Life at Cadence: Celebrating Women's History Month with Girl Geek X!

    Mary Kasik
    Mary Kasik
    To celebrate Women’s History Month in March, Cadence partnered with Girl Geek X for the second time to host another inspiring conference. This virtual, global event featured seven trailblazing leaders at Cadence, who provided motivational advic...
    • 31 Mar 2022
  • Breakfast Bytes: DVCon: There Be Dragons!

    Paul McLellan
    Paul McLellan
    At the recent DVCon, there was a panel session titled SoC Verification Hidden Dragons. The panel was moderated by Brian Bailey of Semiconductor Engineering. The panel consisted of 3 users and a vendor: Mike Chin of Intel. He is a validation engineer...
    • 31 Mar 2022
  • System, PCB, & Package Design : Cadence OrCAD and Allegro 17.4-2019 HotFix SPB17.40.028 is Now Available

    AllegroReleaseTeam
    AllegroReleaseTeam
    The HotFix 028 (QIR4, indicated as 2022 in the application splash screens) update for OrCAD® and Allegro® is now available at Cadence Downloads. This blog post contains important links for accessing this update and introduces some of the main...
    • 31 Mar 2022
  • Analog/Custom Design: Spectre Tech Tips: Using DSPF Post-Layout Netlists in Spectre Circuit Simulator

    Stefan Wuensche
    Stefan Wuensche
    DSPF files are an integral part of post-layout simulations. This blog introduces you to the commands and utilities provided by the Spectre circuit simulator to help you run simulations with DSPF netlists.
    • 31 Mar 2022
  • CFD(数値流体力学): Illinois Blowerは流体シミュレーションによってファンの性能を44%改善

    CFD Japan
    CFD Japan
    石油化学およびその他の産業では、空気の換気や500°C以上の有害な塩化物ガスの処理のためにファンを使用しています。これらのファンの最大運転回転速度は業界標準によって管理され、しばしば制限されています。この制限により、ファンメーカーは所望の圧力出力を得るために、インペラの直径を調整することを余儀なくされます。エンジニアは、結果として得られる設計が特大サイズになったり、重くなったり、製造、試験、輸送にコストがかかったりすることを回避しなければなりません。 イリノイ州ケーリーに拠点を置くIll...
    • 30 Mar 2022
  • Shortage of Chips a Challenge for Vehicle Electrification

    Computational Fluid Dynamics: Shortage of Chips a Challenge for Vehicle Electrification

    Veena Parthan
    Veena Parthan
    Electric Vehicle (EV) market growth, along with the bourgeoning investments in autonomous driving and infotainment systems that constitute the automotive end market, is a top-line revenue boost for chip manufacturers and suppliers. Alternatives to silicon chips for better performance, faster methods of chip production, and various collaborations or partnerships for efficient EV models are expected to mitigate the perturbation…
    • 30 Mar 2022
  • Illinois Blower Increases Fan Performance by 44% with Fluid Dynamics Simulation

    Computational Fluid Dynamics: Illinois Blower Increases Fan Performance by 44% with Fluid Dynamics Simulation

    AnneMarie CFD
    AnneMarie CFD
    Illinois Blower develops and builds custom centrifugal fans and blowers for a variety of worldwide industrial process industries. In order to increase the performance of a centrifugal fan, they performed a 2-phase optimization project using CFD simulation and managed to improve overall performance by 44%. Read here how they did it.
    • 30 Mar 2022
  • Analog/Custom Design: Virtuoso ICADVM20.1 ISR24 and IC6.1.8 ISR24 Now Available

    Virtuoso Release Team
    Virtuoso Release Team
    The ICADVM20.1 ISR24 and IC6.1.8 ISR24 production releases are now available for download.
    • 30 Mar 2022
  • Breakfast Bytes: ESD Alliance CEO Outlook (and the Kaufman Dinner)

    Paul McLellan
    Paul McLellan
    The ESD Alliance has two events coming up in the next couple of months, both of which, as it happens, feature Cadence's CEO Anirudh Devgan, although only one with him in the starring role. CEO Outlook Panel The first event is the CEO Outlook Pane...
    • 30 Mar 2022
  • カスタムIC/ミックスシグナル: Virtuoso Meets Maxwell: RF回路でのカスタム受動デバイス – デバイスかそれともインターコネクトか

    Custom IC Japan
    Custom IC Japan
    'Virtuoso Meets Maxwell' はVirtuoso RF ソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのI...
    • 29 Mar 2022
  • CFD Wind Studies for Ship Superstructures

    Computational Fluid Dynamics: CFD Wind Studies for Ship Superstructures

    AnneMarie CFD
    AnneMarie CFD
    Besides resistance, seakeeping and propulsion, wind loads play an important role in navigation, and wind studies form an essential part of marine engineers' and naval architects' work. Since model tests are expensive and wind tunnel availabilities don't always match project deadlines, CFD simulations become a powerful tool, allowing designers to understand the effects of design changes on their projects quickly and accurately…
    • 29 Mar 2022
  • Breakfast Bytes: The Framework Laptop and Right to Repair

    Paul McLellan
    Paul McLellan
    You might have heard some discussion about "the right to repair" or R2R. Some of this is centered around mobile phones, and some in a place you would not have first thought of: agriculture. Farmers have long been fighting the good fight against bure...
    • 29 Mar 2022
  • Verification: How to Verify JEDEC DRAM Memory Controller, PHY, or Memory Device?

    ssalehab
    ssalehab
    DDR Memory is an important part of a wide array of electronic system designs in various verticals like Data centers, Cloud computing, Aero-Defense, Mobile, or any other consumer devices. These industries continue to demand higher throughput, energy e...
    • 29 Mar 2022
  • Virtuosity: Virtuoso-Innovus Interoperability — Making Trim Shapes Interoperable

    Analog/Custom Design: Virtuosity: Virtuoso-Innovus Interoperability — Making Trim Shapes Interoperable

    Savita Thakur
    Savita Thakur
    Make your Virtuoso designs Innovus ready by ensuring trim and metal shapes follow the P&R routing style and are readable in Innovus.
    • 29 Mar 2022
  • AI Unleashes Chip Designer Productivity

    Life at Cadence: AI Unleashes Chip Designer Productivity

    Kam Kittrell
    Kam Kittrell
    EDA has a history of enabling breakthrough designer productivity. AI in EDA isn’t just making things better. Last year, we launched the biggest, baddest AI in EDA technology called the Cadence®︎ Cerebrus™︎ Intelligent Chip Explorer. It’s a revolutionary product that provides both optimized PPA and productivity benefits.
    • 28 Mar 2022
  • Breakfast Bytes: Cadence: Sustainable by Design

    Paul McLellan
    Paul McLellan
    Last week, Cadence published the Cadence Sustainability Report 2021 (link at the end of this post). As our CEO, Anirudh Devgan, says in the foreword: Our products enable the world’s leading electronics providers to optimize power, space, and e...
    • 28 Mar 2022
  • Computational Fluid Dynamics: This Week in CFD #468

    John Chawner
    John Chawner
    It's a sunny 81 degrees here in Fort Worth as I type this and after going outside for a few minutes after lunch I can tell you it's plenty warm. But not warm enough to melt a diamond which is the Image of the Week in our roundup of CFD news. What els...
    • 25 Mar 2022
  • Verification: Who Inspires You? - An SVG Women's History Month Spotlight

    Melisa
    Melisa
    This month, we join millions celebrating and recognizing the achievements of women. We truly value the women who inspire us and have made a difference in our lives. In honor of Women's History Month, we asked our SVG community to share which wom...
    • 25 Mar 2022
  • Breakfast Bytes: March 2022 Update: Intel Video, India, Apple

    Paul McLellan
    Paul McLellan
    Amazingly, it is already the last Friday in March (and so the last Friday in Q1, it has flown by). So time for one of my update posts where I put stories that are too small to justify an entire blog post, and updates on topics I posted about earlier....
    • 25 Mar 2022
  • Learning and Support: What is IEEE 1500 Wrapper Insertion Flow in Genus Synthesis Solution

    MJ Cad
    MJ Cad
    Are you searching for a scalable standard architecture for enabling test reuse and integration for embedded cores and associated circuitry? Are you looking for a standard that addresses testing strategies for the digital aspects of core designs withi...
    • 25 Mar 2022
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