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Corporate News

Spectre FX Simulator Cuts Intrinsic Semi’s Memory Verification Time by 4X

Intrinsic Semiconductor Technologies, a company transforming the semiconductor industry…

Corporate
Corporate 11 Nov 2025 • 2 min read
newstory , featured , spectre fx , Instrinsic Semi , verification

Corporate News

Cadence Welcomes ChipStack

ChipStack, a leading startup providing agentic AI solutions for chip verification…

Corporate
Corporate 10 Nov 2025 • 1 min read
featured , agentic ai , Xcelium Logic Simulator , AI-Driven Verification

SoC and IP

The Power of Shifting Left: Cadence Accelerating Innovation with Arm

In semiconductor design, projects are remembered for their extremes—legendary successes…

Arif Khan
Arif Khan 7 Nov 2025 • 3 min read
ucie , xcellium , IP , featured , PHY

Corporate News

Accelerating System Design with Real-Time Simulation, Powered by AI Physics

Rising demand for AI infrastructure is driving faster innovation and smarter use…

Corporate
Corporate 28 Oct 2025 • 4 min read
CFD , featured , NVIDIA , accelerated compute , millennium
cdns - all_blogs_categories

  • All 6134
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  • Digital Design 434
  • Learning and Support 56
  • RF Engineering 114
  • SoC and IP 419
  • System, PCB, & Package Design  992
  • Verification 1291
  • Cadence Japan 4

  • CFD(数値流体力学) 45
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  • RF /マイクロ波設計 44
  • Spotlight Taiwan 61
  • The India Circuit 90
  • 定制IC芯片设计 79
  • データセンター 7

  • Whiteboard Wednesdays 253
Blog - Post List
Latest blogs

カスタムIC/ミックスシグナル

Spectre Tech Tips: リークパスによる電流ホットスポットの検出

回路設計において、誤った接続が望ましくないリークパスを引き起こし、結果として電流のホットスポットとなる可能性があります。こういった電流のホットスポットはSpectre…

Custom IC Japan 15 Apr 2021 • less than a min read
Dynamic design checks , Spectre design checks , leakage path detection , Spectre , dyn_dcpath , japanese blog , dyn_subcktpwr

Computational Fluid Dynamics

AeroDelft Pushes the Airline Industry towards a Sustainable Future with Liquid Hydrogen…

AeroDelft is a student team at the forefront of sustainable aviation. While based…

Paul McLellan 15 Apr 2021 • less than a min read
CFD , Computational Fluid Dynamics

Breakfast Bytes

Programming Early Computers Was Very Different from Today

In my post "I Couldn't Imagine Being Too Poor for Servants, or Rich Enough for a…

Paul McLellan 15 Apr 2021 • 10 min read
ibm 1130 , atlas II , icl 1904 , ict 1904 , history

Digital Design

Verifying Design Changes Does Not Have to be Difficult and Tedious — Make it Easier…

You put your design through a multitude of tools for various transformations. Going…

FormerMember 14 Apr 2021 • less than a min read
conformal , formal , Logic Design , Equivalence Checking , Digital Implementation , verification

Breakfast Bytes

Benedict Evans on Tech 2021: Harder Problems and Regulation

This is a continuation of last week's post Benedict Evans' on Tech in 2021 . That…

Paul McLellan 14 Apr 2021 • 6 min read
benedict evans , Internet , regulation

SoC and IP

First Look: Cadence Subsystem SoC for PCIe 5.0

If a picture is worth a thousand words, a video tells you the entire story. Cadence…

Arif Khan 13 Apr 2021 • 1 min read
controller IP , CXL , PCI Express 5.0 , Design IP , IP , PHY , Gen5 , PCIe , semiconductor IP , Design and Verification IP , SerDes , Compute Express Link , SerDes IP , PCI Express

定制IC芯片设计

Virtuoso Video Diary: “Training bytes” 助推知识传播—第4部分

我们生活在一个日趋复杂的世界中,尽可能的使用和组合各种工具及平台,以及其它的可用功能,这对于我们而言至关重要. 在此博客中, 我们将介绍如何使用Spectre Simulation…

Parula 13 Apr 2021 • 2 min read
Chinese blog , Virtuoso , Spectre , Online Support

System, PCB, & Package Design 

BoardSurfers: Training Insights: Setting Up and Using Pin Delays in Constraint M…

Pin delays are used to specify the time delay or length from the internal package…

Niharika1 13 Apr 2021 • 2 min read
17.4 , cadence , BoardSurfers , Cadence Online Support , Constraint Manager , 17.4-2019 , Training Insights , Allegro PCB Editor

System, PCB, & Package Design 

Sigrity and Systems Analysis 2021.1 HF1 Release Now Available

The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2021.1 HF1 release is now available…

SigrityReleaseTeam 13 Apr 2021 • 4 min read
Sigrity and Systems Analysis , Celsius Thermal Solver , Simplified Model , 2D Probes , External Heat Sink , ECXML Export , BNP Viewer , 3D Probes , Clarity 3D Solver , Clarity 3D Workbench , DC Refinement , Cloud Simulation

Breakfast Bytes

NUMECA, Computational Fluid Dynamics...and the America's Cup

What is computational fluid dynamics, or CFD? And what does that have to do with…

Paul McLellan 13 Apr 2021 • 6 min read
CFD , Computational Fluid Dynamics , america's cup , NUMECA

SoC and IP

Taking the Wraps Off: Cadence IP Subsystem for PCIe 5.0

Cadence was the first IP provider to bring controllers for PCI Express (PCIe) 3.0…

Arif Khan 12 Apr 2021 • 2 min read
controller IP , CXL , PCI Express 5.0 , Design IP , IP , PHY , Gen5 , PCIe , semiconductor IP , Design IP and Verification IP , SerDes , Compute Express Link , SerDes IP , PCI , PCI Express

Breakfast Bytes

"Targeting" the Open Compute Project

Target (yes, that Target, the retailer) has an infrastructure and cloud conference…

Paul McLellan 12 Apr 2021 • 3 min read
open compute project , OCP

Breakfast Bytes

Sunday Brunch Video for 11th April 2021

https://youtu.be/D29rGqkkf80 Made in "Hawaii" (camera Ziyue Zhang) Monday: Dynamic…

Paul McLellan 11 Apr 2021 • less than a min read
sunday brunch

Breakfast Bytes

Have You Heard of ISO 21434? You Will

You probably already know what ISO 26262 is. If you don't, then you can find out…

Paul McLellan 9 Apr 2021 • 4 min read
Automotive , iso 21434 , ISO 26262

PCB設計/ICパッケージ設計

Allegro System Capture のやり方で設計する

ロジック設計エンジニアのためのシリーズ 洗練された新しい設計エコシステム、Allegro® System Captureの世界へようこそ。この ASCENT シリーズでは…

SPB Japan 9 Apr 2021 • less than a min read
17.4 , 17.4-2019 , Allegro System Capture , japanese blog

Analog/Custom Design

Virtuoso Video Diary: Knowledge Booster - 5G mmWave Handset System Design

In this blog we would like to let you know – amongst other things - how to implement…

Parula 8 Apr 2021 • 3 min read
training , Cadence training , digital badges , training bytes , Virtuoso , Cadence certified , Virtuoso Video Diary , Custom IC Design , online training , Custom IC

カスタムIC/ミックスシグナル

Virtuoso Video Diary: Virtuoso Visualization and Analysis XLのTabular Graph

読者の皆様、こんにちは。 今回は、Virtuoso Visualization and Analysis XLのエキサイティングな機能であるTabular Graphについてご紹介したいと思います…

Custom IC Japan 8 Apr 2021 • less than a min read
Analog Design Environment , ViVa-XL , custom/analog , ADE Explorer , Analog Simulation , ADE , Virtuoso , ViVA , Virtuosity , japanese blog , Custom IC Design , ADE Assembler

Breakfast Bytes

Cadence/Samsung Automotive Reference Flow

Today, Cadence and Samsung announced the availability of an Automotive Reference…

Paul McLellan 8 Apr 2021 • 6 min read
Automotive , Genus , functional safety , Safety , Samsung , samsung foundry , Innovus , fusa , reliability

Breakfast Bytes

Benedict Evans on Tech in 2021

Benedict Evans used to work in Silicon Valley for Andreesen-Horowitz (a16z) but he…

Paul McLellan 7 Apr 2021 • 6 min read
benedict evans , Internet
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CDNS - Fix Layout Hompage

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