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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Verification

DAC360: Photo blog of DAC 2010 in Anaheim, CA

Click here or on the image below to go to the annotated photo blog of DAC 2010. Images…

• less than a min read
DAC , Specman , TLM , Functional Verification , IBM , OVM , EDA360 , TSMC , Palladium XP , Mike Stellfox , Denali , iPad , AMIQ , Twitter , XJTAG , IEV , Incisive Enterprise Simulator (IES) , Accellera VIP TSC , IFV , IES-XL

SoC and IP

Xilinx unleashes triad of low-power, 28nm FPGA families with very promising characteristics…

Today, Xilinx unveiled three new series of FPGAs all based on 28nm process technology…

• 2 min read

SoC and IP

ProMOS in Taiwan brings up Elpida 63nm process, successfully builds 1-Gbit DDR3 …

Taiwan DRAM maker ProMOS has just announced successful fabrication of 1-Gbit DDR3…

• 1 min read

Verification

DAC Cabbie Taught Me All I Need to Know About Verification

Confidence from competence. Measurement through metrics. Sell without selling. These…

• 4 min read
SystemVerilog , DAC , uvm , ABV , OVM , EDA360 , Register Package , Incisive , Funcional Verification , AMIQ , Twitter , MDV , Accellera VIP TSC , IES , VMM

SoC and IP

Samsung’s 512 Gbyte SSD pushes SATA 3 Gbps to the limit with “30nm class” Toggle…

Samsung just announced that it will be in volume production with a high-speed, 512…

• less than a min read

Verification

What's The Best Way To Reduce SoC Development Costs?

Before I got started with my DAC 2010 customer meetings on Monday morning, I stopped…

• 2 min read
TLM2 , virtual platforms , virtual prototypes , SystemC , DAC 2010

Verification

Hit The Road - DAC!

OK, now that the Design Automation Conference (DAC) seems to be rotating among San…

• 1 min read
DAC , uvm , Functional Verification , OVM

Verification

Snapshots From Day 0 of DAC 2010

Below are some snapshots of some "day 0" events, and last minute DAC preparations…

• less than a min read
DAC , uvm , OVM , Palladium XP

Verification

Advanced Option Brings New Features to Specman/e Users

Great news for Specmaniacs -- a new Specman Advanced Option is being announced at…

• 1 min read
SystemVerilog , DAC , Specman , Functional Verification , Multi-Core , e , team specman , specman elite , Incisive Enterprise Simulator (IES) , IES-XL

SoC and IP

MemCon 2010 registration closing in on 400 attendees. Theme is "Roadmap: GHz DDR3…

We’re still more than a month away from MemCon 2010 in Santa Clara (July 28) and…

• 1 min read

Verification

A New Toy for UVM Geeks

Wasn't it great when you were a kid at Christmas, and you got all those new toys…

• 1 min read
SystemVerilog , methodology , Verification methodology , metric driven verification (MDV) , Functional Verification , Incisive , MDV

SoC and IP

Questions for the DAC Pavilion Panel on multicore design

As I wrote yesterday, I’ll be chairing a Multicore panel at DAC in Anaheim on Monday…

• 1 min read

Verification

Cadence Contributes ESL Methodology To TSMC Reference Flow 11

The EDA360 industry vision document shows how growing complexity and application…

• 3 min read
ECO , OIP , C to Silicon , TSMC , system , ESL , verification

SoC and IP

Don’t miss the multicore Pavilion panel discussion at DAC on Monday, June 14

I’ll be moderating the Pavilion panel titled “The Multiplier Effect: Developing Multi…

• less than a min read

SoC and IP

Denali to demo new PureSpec 2.0 verification-management technology at DAC 2010

This news is a bit far afield for Denali’s Memory Blog, but many of our blog readers…

• 1 min read

SoC and IP

Making SSDs, the TweakTown video: See how A-DATA makes SSDs based on SandForce SF…

TweakTown’s crew visited A-DATA’s manufacturing floor during Computex in Taiwan and…

• 1 min read

SoC and IP

ST Microelectronics’ SPEAr1300 Embedded Processor family employs Denali Databahn…

Last month, this blog described the new SPEAr1300 Embedded Processor family from…

• less than a min read

Verification

Accelerating Metric-Driven Verification With “Hotswap” on Verification Computing…

For a while now, Cadence has been providing leading verification solutions and methodologies…

• 1 min read
emulator , DAC , Acceleration , Palladium , hotswap , Emulation , hot swap , metric , metric-driven verification , MDV

Analog/Custom Design

ARM And Cadence Get To The “Core” Of Mixed-Signal Design

An increasing number of analog and mixed-signal designs in automotive, power management…

• 4 min read
Cortex , analog , Mixed-Signal , Virtuoso , Cortex-M0 , mixed signal , ARM
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