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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
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Breakfast Bytes

What’s for Breakfast? Preview September 19th to 23rd (video)

https://youtu.be/KKiIDaN-3CE Monday: At CDNLive Boston I moderated a panel session…

• less than a min read
cdnlive tel aviv , Paul McLellan , CDNLive , debug , mellanox , VIP , MIPI , Power Integrity , i2c , cdnlive boston , mipi devcon , Indago , Signal Integrity , cdnlive israel , I3C , what's for breakfast? , protocol verification , Breakfast Bytes , verification

Breakfast Bytes

Emulation Productivity: Beyond the Specs

At CDNLive in Boston, Andrew Ross of AMD presented a wealth of practical information…

• 5 min read
CDNLive , palladium z1 , Protium , Palladium , cdnlive boston , Emulation , FPGA prototyping , Breakfast Bytes

Academic Network

Increasing Functional Verification Coding Process Efficiency

In EDA you traditionally have to know several modelling languages for several domains…

• 3 min read
eclipse , Cadence Academic Network , Functional Verification , DVT , Coding Efficiency

Breakfast Bytes

Everything That's New About Ethernet

IEEE 802.3 is the standard number for various flavors of Ethernet. With Ethernet…

• 6 min read
Ethernet standards , Ethernet , 802.3 , IEEE , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Training Different Networks Using Hierarchical CNN

In this week's Whiteboard Wednesdays video, Michelle Mao follows up on last week…

• less than a min read
Whiteboard Wednesdays , IP , Tensilica

Breakfast Bytes

DARPA: All Must Have Prizes

At CDNLive Boston, the invited keynote was by Dr. Bill Chappell of DARPA's Microsystems…

• 4 min read
CDNLive , cdnlive boston , robotics , autonoous vehicles , craft , microsystems technology office , darpa

Breakfast Bytes

Electronic Design Automation Handbook

Way back in 2006, Luciano Lavagno, Lou Scheffer, and Grant Martin, all then at Cadence…

• 4 min read
TCAD , Electronic Design Automation , system design , EDAC , Testing , implementation , Circuit Design , process design , Breakfast Bytes , verification , book

Breakfast Bytes

Facebook's Aquila Flies...and OpenCellular

In Barcelona in February I attended a "keynote' with Mark Zuckerberg which was actually…

• 4 min read
aquila , Facebook , opencellular , zuckerberg , internet.org

Breakfast Bytes

What’s for Breakfast? Preview September 12th to 16th (video)

https://youtu.be/eDeD0mg7D54 Monday: My review of Electronic Design Automation…

• less than a min read
CDNLive , palladium z1 , AMD , H.265 , IEEE 802.3 , cdnlive boston , Ethernet , Emulation , codec , netflix , h.264 , vp9 , video codec , darpa

Breakfast Bytes

Cadence's History with MIPI

I talked last week to Kevin Yee, Sachin Dhingra, and Moshik Rubin about the history…

• 6 min read
Automotive , MIPI , mipi devcon , mobile

Whiteboard Wednesdays

Whiteboard Wednesdays - Benefits of Cadence Hierarchical CNN Design

In this week's Whiteboard Wednesdays video, Michelle Mao talks about Cadence hierarchical…

• less than a min read
Whiteboard Wednesdays , IP , Tensilica , CNN

Breakfast Bytes

SiFive: a RISC-V Fabless Semiconductor Company

A couple of weeks ago I talked to Krste Asanović and Jack Kang of SiFive. Jack is…

• 3 min read
risc-v , fabless , sutter hill ventures , freedom unleashed , freedom everywhere , sifive , foundry

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? New Concurrent Team Design Capability (Reason 2…

Use teamwork to get off the critical path! When (not if) change happens or scope…

• 3 min read
Allegro 17.2 , Symphony , Real Time Design , PCB design , Why Move Up to 17.2

System, PCB, & Package Design 

Cadence Online Support — Empowering Learning! New Features from July 2016

Lots of documents are posted on Cadence Online Support on regular basis. Let us take…

• 2 min read
cadence online , "PCB design" , application note , Allegro

Breakfast Bytes

CDNLive Boston Overview

CDNLive Boston took place last week. It is really CDNLive East Coast, and there were…

• 6 min read
CDNLive , Power Integrity , cdnlive boston , Signal Integrity , Breakfast Bytes

Breakfast Bytes

RISC-V Gathering Momentum

I've been writing quite a bit about RISC-V (pronounced "risk five") since I think…

• 4 min read
krste asonovic , risc-v , codasip , NVIDIA , google , andes , cortus , Breakfast Bytes , sifive , hp enterprise

Breakfast Bytes

Happy Birthday, HP 12c—35 Years and Counting

Last year was the 50th anniversary of Moore's Law. One consequence of Moore's Law…

• 3 min read
hewlett-packard , hp 12c , CMOS , hp12c , calculator , Breakfast Bytes

Verification

DisplayPort 8K in Olympics 2020

If you’re anything like me, you’ve spent the last couple of weeks glued to the TV…

• 3 min read
Verification IP , VIP , DisplayPort , Design and Verification IP , Olympics

Breakfast Bytes

What’s for Breakfast? Preview September 6th to 9th (video)

https://youtu.be/lD8VFUNds7o Monday: Labor Day. Tuesday: CDNLive Boston. I…

• less than a min read
risc-v , acquila , CDNLive , MIPI , Power Integrity , open cellular , cdnlive boston , mipi devcon , Facebook , Signal Integrity , sifive
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