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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

BoardSurfers: Installation Know-How: Configuring OrCAD and Allegro Installations…

Often, you install the Cadence products with default settings and that suffices to…

• 4 min read
Installation Know-How , 17.4 , BoardSurfers , Allegro OrCAD Installer , 17.4-2019 , OrCAD , installation , Allegro

Breakfast Bytes

China, US, Europe: Everybody's Got a CHIPS Act

I ran across a very interesting report from the Semiconductor Industry Association…

• 5 min read
asml , China , SIA , US CHIPS Act , Europe Chips Act

Breakfast Bytes

Generic and Open PDKs

One challenge that educators and researchers face is that they typically have no…

• 4 min read
Open PDK , openroad , google , PDK , efabless

Computational Fluid Dynamics

Simulate Wind Turbine Blade Aerodynamics Using High-Quality Automated Meshing

Dr. Galih Bangga, a scientist with a forte in wind energy research, from the Institute…

• 3 min read
CFD , Meshing Monday , Mesh metrics , Automated meshing , engineering , simulation software , Cadence Pointwise , Mesh Generation , Meshing

Breakfast Bytes

Sunday Brunch Video for 13th February 2022

https://youtu.be/_Rt6kAURffU Made in Rancho San Antonio County Park (camera Carey…

• less than a min read
sunday brunch

Breakfast Bytes

January Update

I realize that it is February, but I was sick late January and so I never wrote this…

• 5 min read
Intel , risc-v , NVIDIA , update , ARM , agriculture

Learning and Support

Webinar Invitation: Enhance your Design Power with Joules

Want to take a tour of this powerful power estimation tool and gear up so you understand…

• 2 min read
Cadence Support Portal , Cadence support , cadence learning and support

Breakfast Bytes

CadenceLIVE Silicon Valley 2022: You Can Be Part of the Event

CadenceLIVE Silicon Valley is scheduled for June 8 and 9, and currently it is planned…

• 1 min read
cadencelive

Computational Fluid Dynamics

Go Zero Emission with Plug-In Buoys for Ships

There has been persistent traffic in the American ports with tons of containers stacked…

• 2 min read
marine traffic , Mooring , shorepower , buoys , GHG emissions

カスタムIC／ミックスシグナル

Spectre Tech Tips: Spectre 電圧ドメイン・チェック

Spectre®回路シミュレータは、過渡解析やその他の解析を実行することなく、典型的なセットアップや設計上の問題を特定することができる、スタティックまたはトポロジー…

• less than a min read
Spectre 21.1 , Analog Simulation , Spectre Circuit Simulator , japanese blog , Spectre X Simulator

Breakfast Bytes

DATE 2022 Now Fully Virtual

As you can tell from the title of my DATE 2022 preview post Save the DATE: Design…

• 1 min read
DATE , date 2022 , design and test europe

Verification

Optimizing CPU Time, TAT, and Disk Space using Cadence Xcelium Advanced Technologies…

Design for Testability (DFT) simulation is crucial to the SOC design process: rapid…

• 8 min read
System Design and Verification , PPA , Disk Space optimization , xcelium , HREF

Analog/Custom Design

Virtuoso ICADVM20.1 ISR23 and IC6.1.8 ISR23 Now Available

The ICADVM20.1 ISR23 and IC6.1.8 ISR23 production releases are now available for…

• 2 min read
Analog Design Environment , Cadence blogs , Virtuoso RF Solution , IC Release Announcement blog , Virtuoso RF , Layout EXL , Virtuoso Analog Design Environment , Virtuoso , ICADVM20.1 , IC Release Blog , Virtuoso Layout Suite , Custom IC , IC6.1.8 , Floorplanner , Allegro , ADE Assembler

Life at Cadence

4 Ways Computational Software Is Transforming System Design and Hardware Design

System and Hardware Design Strides and Challenges Electronics systems are changing…

• 7 min read
computational software

Breakfast Bytes

The Return of Breakfast Bytes

If you are an avid follower of Breakfast Bytes, and of course, you should be, you…

• 2 min read
covid

SoC and IP

High-Speed 112G Design and COM Dependencies

The design impairments such as SoC packaging, package-to-board impedance mismatch…

• 5 min read
high-speed , 112g , SerDes , SerDes IP , COM Dependencies , Log-Reach

Life at Cadence

Volunteering in Today’s World

Cadence recently announced its sixth Season of Giving. Giving back is a special part…

• 3 min read
Culture , Cadence Cares , cadence , giving back , Season of Giving , LifeAtCadence , life at cadence , volunteer , cadence emea

System, PCB, & Package Design 

System Analysis Knowledge Bytes: Tips for Accelerating Power Signoff in Chip-package…

This blog discusses PLOC grouping optimization which provides the flexibility in…

• 4 min read
Voltus IC Power Integrity Solution , Chip-package Co-analysis , PLOC GROUPING OPTIMIZATION , Sigrity XtractIM , PLOC

The India Circuit

Mentor Story: Roli Sinha - Cadence Scholarship Program

Introduced five years ago, the Cadence Scholarship Program is the flagship CSR program…

• 3 min read
CadenceCares , CadenceScholarshipProgram , cadence , Cadence India
CDNS - Fix Layout Hompage