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SoC and IP

The Power of Shifting Left: Cadence Accelerating Innovation with Arm

In semiconductor design, projects are remembered for their extremes—legendary successes…

Arif Khan
• 3 min read
ucie , xcellium , IP , featured , PHY

Corporate News

Accelerating System Design with Real-Time Simulation, Powered by AI Physics

Rising demand for AI infrastructure is driving faster innovation and smarter use…

Corporate
• 4 min read
CFD , featured , NVIDIA , accelerated compute , millennium

Analog/Custom Design

Virtuoso Studio IC25.1 ISR2 Now Available

Virtuoso Studio IC25.1 ISR2 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Data Center

Innovation in Data Center Design and Operations: Highlights from Thésée Event

The Thésée event brought together key partners like France Télévisions, Thésée, Cadence…

Veena Parthan
• 5 min read
featured , Thésée Event , data center , Cadence Reality Digital Twin Platform
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Academic Network

How to Get Remote Access to Cadence Academic Tools and Licenses

With the ever-evolving workplace and classroom, we know that the way we work and…

• 4 min read
Europractice , Cadence Academic Network , remote access , EDA , CMC Microsystems , university program

System, PCB, & Package Design 

IC Packagers: Identify Your Components

We’ve all seen bar codes and the more modern QR codes. They’re everywhere you go…

• 2 min read
Allegro Package Designer , Allegro PCB Editor

Breakfast Bytes

2020 Is the Year of DDR5

I talked recently to Marc Greenberg, one of Cadence's experts on the memory market…

• 3 min read
ddr5 , Memory , DDR4

Digital Design

Library Characterization Tidbits: Validating Libraries Effectively

In this blog, I will brief you about two very useful Rapid Adoption Kits (RAKs) for…

• 3 min read
Liberate LV , timing validation , Digital Implementation , interpolation error , library validation , RAKs

Analog/Custom Design

Virtuoso Meets Maxwell: Help with Electromagnetic Analysis - Part V

Here is another blog in the multi-part series that aims at providing in-depth details…

• 9 min read
EM Analysis , ICADVM18.1 , VRF , Virtuoso Layout EXL , ports , Virtuoso RF , Electromagnetic analysis , Virtuoso , Virtuoso Layout Suite , Custom IC

Breakfast Bytes

Turing Award: Ed Catmull and Pat Hanrahan

Last week, the ACM announced this year's Turing Award would go to Pat Hanrahan and…

• 5 min read
vlsi technology , turing award , graphics

Breakfast Bytes

Sunday Brunch Video for 22nd March 2020

https://youtu.be/b7ixzahr85s Made on my balcony (camera Carey Guo) Monday: Another…

• less than a min read
sunday brunch

Breakfast Bytes

Netflix and C...adence

Earlier in the week, I wrote about a couple of videos from Intel, about semiconductor…

• 1 min read
sunday brunch , video , intelligent system design

Breakfast Bytes

RSA 2020: From Sulu to Penn & Teller

I attended the RSA Conference in San Francisco recently. I guess that is going to…

• 6 min read
security , rsa conference , rsa

System, PCB, & Package Design 

IC Packagers: Design Element Label Management

A few weeks ago, we talked about template text labels for design-specific information…

• 4 min read
Allegro Package Designer , Allegro PCB Editor

System, PCB, & Package Design 

BoardSurfers: Creating Footprints Using Templates in Library Creator

With ECAD-MCAD Library Creator, you can easily create footprints for your parts using…

• 3 min read
Library Creator , 17.4-2019 , ECAD-MCAD Library Creator , PCB design

Breakfast Bytes

How Intel Manufactures Chips

I happened to be looking for something on YouTube recently when I came across this…

• 3 min read
Intel , fab

定制IC芯片设计

Virtuosity：回顾定制IC芯片设计博客的黄金时代

如果您错过了2019 发布的Virtuosity, Virtuoso Meets Maxwell 和Virtuoso Video Diary等博客专栏，或者您想了解已发布ISR中的增强功能…

• less than a min read
Chinese blog , ICADVM18.1 , Automated Device-Level Placement and Routing , Virtuoso RF , Layout EXL , Electromagnetic analysis , Virtuoso , Virtuosity , Custom IC Design , Virtuoso Layout Suite , Custom IC

Analog/Custom Design

Virtuosity: Device Arrays in the Automated Device Placement and Routing Flow

Since the release of the Automated Device Placement and Routing solution last year…

• 3 min read
Modgen On Canvas , ICADVM18.1 , MODGEN , Automated Device-Level Placement and Routing , APR Modgen , Advanced Node , auto device array , APR , Auto P&R , advanced nodes , ada , Custom IC Design , Custom IC

System, PCB, & Package Design 

New 3D Analysis Engine Offers Faster, More Accurate Simulations at Lower Cost

A multi-CPU architecture running on both cloud and on-premise computers can better…

• 6 min read
PCB , IC , 3D full wave extraction , 3D analysis , IC package design , Sigrity , High Speed design , clarity

Breakfast Bytes

Digital Full Flow for 5/7nm

One constant in the semiconductor and EDA industries is, of course, Moore's Law.…

• 4 min read
Genus , P&R , Tempus , Voltus , Innovus , digital full flow , Synthesis , full flow

Analog/Custom Design

Virtuoso Meets Maxwell: Bumps, Bumps.... Where Are My Bumps?

Bumps are central to the Virtuoso MultiTech Framework solution. Bumps provide a connection…

• 3 min read
ICADVM18.1 , Edit-in-Concert , Co-Design , Virtuoso Meets Maxwell , Virtuoso RF , Layout EXL , stacked solution , Custom IC Design , bumps

Breakfast Bytes

Another Year of CadenceLIVE—with Updated Schedule

It's not strictly true that it is another year of CadenceLIVE since we called the…

• 3 min read
CDNLive , cadencelive

Verification

RAK Attack: Better Driver Tracing, Faster Palladium Build Time, UVM Register Map…

Looking to learn? There's a bunch of new RAKs (Rapid Adoption Kits) available online…

• 2 min read
Rapid Adoption Kit , IXCOM , RAK , Indago , JasperGold
CDNS - Fix Layout Hompage