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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
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Latest blogs

System, PCB, & Package Design 

System Analysis Knowledge Bytes - Optimizing LPDDR5X Performance with Sigrity X

This blog post explores the capabilities of Cadence Sigrity X Advanced SI in designing…

• 5 min read
Sigrity and Systems Analysis , TopXp , PBA , DDR interface , Sigrity X , system analysis , measurement , license , SPB , ddrx , lpddr5x , Sigrity , High Speed design , simulation , Advanced SI

SoC and IP

Time-of-Flight Decoding with Tensilica Vision DSPs

Today, let's break down time-of-flight (ToF) and how Tensilica Vision DSPs can be…

• 1 min read
IP , Consumer Electronics , cadence , video , Tensilica DSPs , ip cores , Tensilica , vision , semiconductor IP , cadencelive , imaging , image processing

Verification

eMMC: The Embedded Storage Powering On-Device AI

In today's world of increasingly intelligent devices, efficient and reliable storage…

• 2 min read
Verification IP , VIP , verification

Verification

Using PSS Registers with Perspec for Portable Programming Sequences

When you use Cadence’s Perspec System Verifier and the Portable Test and Stimulus…

• 6 min read
Perspec , perspec system verifier , pss

Corporate News

Cadence to Power the Fourth Industrial Revolution in Collaboration with NVIDIA

The convergence of artificial intelligence (AI), robotics, and the internet of things…

• 1 min read
NVIDIA , Protium , Palladium , designed with cadence

SoC and IP

Cadence San Jose Hosts JEDEC LPDDR Task Group Meeting

Low-power DDR ( LPDDR ) SDRAM has been one of the most widely used memories in the…

• 2 min read
Verification IP , Design IP , IP , VIP , JEDEC , LPDDR PHY IP , DRAM , LPDDR Controller IP , Design IP and Verification IP , Lpddr6

Analog/Custom Design

Custom Analog IP Migration in Virtuoso Studio

Join Cadence Training and presenters from our CIC experts for this free technical…

• 3 min read

System, PCB, & Package Design 

Efficient Automotive Electronic Component Design and Analysis

In the automotive industry, there is zero tolerance for field failures, as human…

• 3 min read

RF /マイクロ波設計

Cadence Microwave Office によるミックスモード・アウトフェージング増幅器の設計

近年の通信システムにおいて、基地局増幅器は高周波化・広帯域化が進み、高効率デバイスの開発が進められています。その中で負荷変調を用いた高効率化・広帯域化が注目されています…

• less than a min read
RF Simulation , Circuit simulation , AWR Design Environment , awr , RF design , microwave office , japanese blog , scripting

Verification

NOP Flit Payload: A Dedicated Debug Channel

Modern PCIe systems are complex, with high-speed data transfer and intricate protocols…

• 3 min read
NOP Flit Payload , debug , PCIe , PCIe 6.0 , PCI Express , Debug Chunk , NOP.Debug Flit Payload

Digital Design

Silicon Skylines: Crafting the Future of Electronics

The world of Electronic Design Automation (EDA) is fascinating, where we transform…

• 4 min read
electronic system design , Electronic Design Automation , training , training bytes , Semiconductor , online training

中文技术专区

Cadence 率先推出 eUSB2V2 IP 解决方案，助力打造高速连接新范式

为了提供更好的用户体验，包括高质量的视频传输、更新的笔记本电脑（例如最新的 AI PC）和其他前沿设备，都需要 5 纳米及以下的先进节点 SoC，以达成出色的功耗…

• less than a min read
eUSB2v2 , IP , TSMC , USB

Corporate News

NepTech – Tackling Marine Decarbonization with Fidelity CFD

Maritime transport is the backbone of international trade. It’s responsible for transporting…

• 2 min read
CFD , FINE Marine , designed with cadence , Fidelity CFD

Corporate News

Cadence and Kyle Juszczyk Partner with Veggielution for Earth Month Event

Forty volunteers from Cadence and the San Francisco 49ers participated in farm projects…

• 2 min read
Cadence Giving Foundation , STEM , featured , NetZero , Earth Month , earth day , 49ers , AI for All

SoC and IP

HBM4 Boosts Memory Performance for AI Training

The recent HBM4 specification announced by JEDEC is great news for developers of…

• 2 min read
Design IP , JEDEC , hbm4 , memory IP , AI training , data centers

System, PCB, & Package Design 

Sigrity and Systems Analysis 2024.1 HF2 Release Now Available

The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2024.1 HF2 release is now available…

• 5 min read

Cadence Japan

ケイデンス、業界初のeUSB2V2 IPソリューションを発表

ケイデンスは、業界初のeUSB2V2 IPソリューションを発表しました。詳細はこちらをご覧ください。

• less than a min read
news story , TSMC , USB設計 , japanese blog

System, PCB, & Package Design 

Multiphysics Analysis Portfolio Continues to Grow

Cadence's multiphysics system analysis (MSA) portfolio grew in both depth and breadth…

• 3 min read
electromagnetics , CFD , Celsius Thermal Solver , Voltus IC Power Integrity Solution , system analysis , data center , Computational Fluid Dynamics , SI/PI Analysis , fidelity , Digital Twins , Thermal Analysis , Sigrity , Clarity 3D Solver , millennium , EMX Solver , BETA CAE Systems , multiphysics , Cadence Reality DC

Corporate News

CadenceLIVE Silicon Valley 2025: Transforming Tomorrow, Today

Are you ready to witness a transformation that redefines the very foundation of technological…

• 3 min read
Automotive , featured , innovation , physical ai , computational software , cadencelive , AI
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