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Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Life at Cadence

My Life at Cadence: Sebastien Caussette

At Cadence, our strength as a company comes from our innovative ideas, collaborative…

• less than a min read
Insights on Culture , Culture , cadence , GPTW , my life at cadence , great place to work , life at cadence , cadence emea

The India Circuit

Join Cadence at DVCon India 2021 Next Week!

It's almost time for the event that Design and Verification engineers have been waiting…

• 1 min read
DVCon India , Accellera

System, PCB, & Package Design 

(P)SpiceITUp: Using Curve-Fitting to Optimize a Design

If you are interested in the performance of a circuit that can be best described…

• 5 min read
17.4 , OrCAD Capture , PSpiceA/D , (P)SpiceItUp , 17.4-2019 , PCB design , PSpice Advanced Analysis

Breakfast Bytes

Cadence Endowments in Academia

Cadence has a long history of involvement with academia, going all the way back to…

• 5 min read
MIT , Stanford , Berkeley , cmu , fellowships

PCB設計／ICパッケージ設計

ASCENT: 17.4-2019 Hotfix 019以上に移行すべき更なる理由とは

前回のブログ に続き、 Hotfix 019 で新たに追加された興味深い変更点を見てみましょう。Allegro® System Captureは、一人で作業する設計者でも…

• less than a min read
System Capture , Allegro Schematic , 17.4 , Allegro Pulse , Allegro System Capture , japanese blog , ASCENT , 17.4-QIR3 , Allegro

Verification

From AMBA ACE to CHI, Why Move for Coherency?

Introduced back in 2011, ACE (AXI Coherency Extensions) grew from existing AXI protocol…

• 2 min read
Verification IP , ACE VIP , Functional Verification , VIP , coherency , CHI VIP

Breakfast Bytes

Automotive Supply Chains

I'm sure you've heard that there are lots of supply chain issues. Container ships…

• 6 min read
Automotive , semi , ic insights

Spotlight Taiwan

Cadence Sigrity X獲選亞洲金選獎(EE Awards Asia)年度EDA最佳產品獎

Cadence Sigrity X日前獲選為2021年亞洲金選獎(EE Awards Asia) EDA/IP組別台灣區與亞洲區年度最佳產品獎(Best Product…

• less than a min read
Sigrity X , system analysis , taiwanese blog

Spotlight Taiwan

超越摩爾定律 Cadence以Cerebrus與Integrity 3D-IC擘劃新局

Cadence『智慧系統設計』的策略方向下聚焦數位全流程的創新 – 今年推出驅動晶片設計及晶片尺寸未來的『Cerebrus智慧晶片設計工具』及『Integrity…

• less than a min read
cerebrus , Digital Implementation , taiwanese blog , intelligent system design , integrity3DIC

Breakfast Bytes

Sunday Brunch Video for 5th December 2021

https://youtu.be/MPbxTioQ2EI Made in Rancho San Antonio Open Space Preserver (camera…

• less than a min read
sunday brunch

Computational Fluid Dynamics

This Week in CFD

Hard to believe it's already December and 11/12ths of a year's worth of CFD is behind…

• 1 min read
CFD , Pointwise , Computational Fluid Dynamics , fluid dynamics

Breakfast Bytes

DAC Preview

The annual Design Automation Conference (DAC) is coming up December 5th to 9th, next…

• 4 min read
DAC , 58DAC , Design Automation Conference

System, PCB, & Package Design 

ASCENT: Managing Designs with Evolving Libraries

Components, or parts, are the basic building blocks of a PCB design. It is of utmost…

• 4 min read
System Capture , 17.4 , 17.4-2019 , design , ASCENT , library , Schematic , Allegro

Analog/Custom Design

Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 12 - Using Quview and…

This blog shows how Quantus Geometry Viewer (Quview) can be used to view various…

• 5 min read
blended , Pegasus Verification System , pegasus , Quantus Connectivity Checker , training , Cadence training , digital badges , training bytes , Virtuoso , Cadence certified , Virtuoso Video Diary , Cadence Education Services , Quantus , Custom IC Design , online training , Quview

Life at Cadence

Commemorating Our Veterans During Veterans Day

Creating an environment of respect and appreciation for one another is a core element…

• 2 min read
inclusion , Culture , Veterans Day , cadence , Military , marines , air force , army , veterans , diversity , life at cadence , veteran , navy

Breakfast Bytes

November Update: Automotive, Graviton 3, Images, New Fab, and More

Because of the Thanksgiving break (and me taking the whole week off), I skipped the…

• 6 min read
graviton 3 , Samsung , graviton , gf , aws , photonics , GlobalFoundries , general motors , Ford

Computational Fluid Dynamics

Unsteady Simulation Of Hydraulic Turbines, Vortex Cores Display And Much More In…

The newest release of the Cadence Omnis CFD environment is available now and brings…

• 1 min read
CFD , Automotive , turbomachinery , webinars , Computational Fluid Dynamics , fluid dynamics , CFD Applications , simulation software , Mesh Generation , Omnis

System, PCB, & Package Design 

System Analysis Knowledge Bytes: SPEEDEM Gets a New Home in Layout Workbench

Sigrity SPEEDEM technology is uniquely equipped to let you perform a broad range…

• 5 min read
Sigrity and Systems Analysis , Power Integrity , IC package design , Signal Integrity , Sigrity SPEEDEM , Layout Workbench

System, PCB, & Package Design 

Sigrity and Systems Analysis 2021.1 HF4 Release Now Available

The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2021.1 HF4 release is now available…

• 1 min read
Sigrity and Systems Analysis , Needle Array Netlist , Sigrity XtractIM
CDNS - Fix Layout Hompage