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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

PCB設計／ICパッケージ設計

Boardsurfers: Allegro DesignTrue DFM Rule Aggregatorで複数のDFMルールをマージ

一つの設計会社が複数の基板製造メーカーと連携することは珍しくありませんが、製造メーカーは恐らく、それぞれが異なるDFMルールセットを必要とするはずです。そこで、設計会社の慣習として…

• 1 min read
Allegro DesignTrue , PCB Editor , 17.4-2019 , japanese blog , Allegro PCB Editor , DFM

Breakfast Bytes

Tensilica FloatingPoint DSP Family

Recently, Cadence announced the availability of the Tensilica FloatingPoint DSP family…

• 3 min read
floating-point , Tensilica , floatingpoint

Life at Cadence

My Life at Cadence: Ludovic Perier

Cadence was recently recognized as Fortune and Great Place to Work® as one of the…

• 1 min read
Culture , GPTW , my life at cadence , great place to work , life at cadence , cadence emea

Breakfast Bytes

Cadence Report: "Hyperscale Computing Will Positively Impact Me within Five Years…

Do you know what hyperconnectivity is? It is already affecting you, whether you know…

• 6 min read
hyperscale data center , cloud , hyperscaler , hyperconnectivity

Analog/Custom Design

Virtuoso Meets Maxwell: Get Connected!

One of the strengths of the Virtuoso RF solution is the ability to handle connectivity…

• 4 min read
IC , package , cross-fabric , Edit-in-Concert , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Package Design in Virtuoso , ICADVM20.1 , Custom IC Design , Virtuoso Layout Suite EXL , RAKs , bump , VMM

Breakfast Bytes

Sunday Brunch Video for 27th June 2021

https://youtu.be/nD_AYa2AbfU Made in my car (camera: my car's phone mount) Monday…

• less than a min read
sunday brunch

Computational Fluid Dynamics

This Week in CFD

It's Friday which means it's time to take a look back at what happened in the CFD…

• less than a min read
CFD , geometry modeling , Pointwise , Computational Fluid Dynamics , CAD , Omnis

Breakfast Bytes

June Update: PCIe 6.0, Ransomware, Mars, Turing Award...and CadenceLIVE

I have decided to put these "Update" posts that I do from time to time on a more…

• 4 min read
ransomware , turing award , pcie 6 , PCIe , turing , Mars

Analog/Custom Design

Virtuosity: Mystery Behind the .simrc File and Netlist Customization

Read on to know the usefulness of the .simrc file and how and when it is picked by…

• 7 min read
ic design methodology , AMS , Analog Design Environment , ic analog design , Cadence blogs , programming , mixed-signal simulators , custom/analog , Analog Simulation , analog , Mixed-Signal , full custom ic design , Virtuoso Analog Design Environment , Virtuoso , Spectre , Virtuosity , cadenceblogs , ICADVM20.1 , Circuit Design , mixed signal , analog design , Custom IC Design , IC6.1.8 , SKILL , Schematic , Analog IC Design , custom design technology , custom integrated circuit

Breakfast Bytes

Quantum Computing with Spectre's Ultra-Low Temperature Models

Equal1 has just announced a breakthrough in quantum computing with a fully integrated…

• 6 min read
quantum computing , 22fdx , gf , GlobalFoundries , FD-SOI

PCB、IC封装：设计与仿真分析

动态电压和频率调节如何影响功耗

本文要点 降低 CPU 或 GPU 功耗的技术有许多，这些技术聚焦软件/固件层面、系统层面和晶体管架构层面 其中两种降低功耗的技术为：动态电压和频率调节，即调整电源电平…

• less than a min read
PI , Chinese blog , 电源完整性 , 仿真分析 , GPU , 功耗 , Sigrity X , 中文 , 系统分析 , Sigrity , CPU

System, PCB, & Package Design 

BoardSurfers: Training Insights: A Comprehensive Solution for Setting Up PCB Design…

PCB design complexities increase with the increase in the number of parts and layers…

• 3 min read
17.4 , BoardSurfers , PCB Editor , 17.4-2019 , PCB design , Training Insights , Allegro PCB Editor , Allegro

Breakfast Bytes

New Banknote with Alan Turing: "This Is a Foretaste of What Is to Come, and the Shadow…

Today is Alan Turing's birthday. More to the point, today the first £50 banknotes…

• 5 min read
bank of england , bletchley park , computer science , turing

Digital Design

Pegasus: Get your Wings: Pegasus Run Controls

Have you ever been in a situation where the run has started and you realize that…

• 4 min read
Pegasus Verification System , Run Control Commands , pegasus , Pegasus Run Control , signoff

Computational Fluid Dynamics

Overcoming Geometry Model Challenges for CFD Mesh Generation

I have often said that geometry modeling is to mesh generation what turbulence modeling…

• 7 min read
CFD , geometry modeling , Pointwise , Computational Fluid Dynamics , CAD , Mesh Generation , Computer Aided Design

Computational Fluid Dynamics

New Release - Omnis Version 5.1 Is Out Now!

Want to see it in action? VIEW WEBINAR RECORDING The newest version of the…

• 2 min read
CFD , Computational Fluid Dynamics , Omnis

Breakfast Bytes

Jim Hogan and Ed McCluskey Named Honorees of the Phil Kaufman Hall of Fame

In February of this year, the ESD Alliance and IEEE CEDA announced the creation of…

• 4 min read
ieee ceda , Jim Hogan , jed mccluskey , esd alliance

Verification

PIPE SerDes Architecture for PCIe Gen 5 and Beyond

Intel PIPE (PHY Interface for PCIE, SATA, USB3.1, DisplayPort and USB4) specification…

• 2 min read
Intel , IP verification , PHY , pcie 5 , VIP , PCIe , SerDes , pcie gen6

Computational Fluid Dynamics

This Week in CFD

It's a short week here at Cadence CFD as we celebrate the Juneteenth holiday today…

• less than a min read
CDNS - Fix Layout Hompage