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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

Analog/Custom Design

The Leader of the Orchestra: Getting Started with Virtuoso ADE Verifier

The members of an orchestra are often great virtuosi on their own instruments, but…

• 3 min read
verifier , Virtuoso ADE Verifier , Virtuoso Analog Design Environment , Analog Design Environment

Breakfast Bytes

Patents and Standards, Managing the Challenge

One challenge with standards is the desire to avoid unknowingly incorporating patents…

• 5 min read
vlsi technology , Rambus , ieee patent policy , GSM , loa , patent , IEEE-SA , IEEE , letter of assurance , Breakfast Bytes , standard

Breakfast Bytes

Andrew Kahng on PPAC Scaling Below 7nm

Last week Dr. Andrew Kahng came to town. He was at CDNLive, where his presentation…

• 5 min read
ucsd , roadmap , ITRS , Cadence Academic Network , kahng , andrew kahng , 5nm , 7nm , power

Academic Network

Academic Track Makes Its Debut at CDNLive Silicon Valley

For the first time at CDNLive Silicon Valley, Cadence Academic Network hosted an…

• 2 min read
Cadence Academic Network , CDNLive , academia

Breakfast Bytes

Phil Moorby and the History of Verilog

Last Saturday there was a gala event at the Computer History Museum in Mountain View…

• 6 min read
verilog-xl , gateway design automation , SystemVerilog , Gateway , Phil Moorby , Verilog , computer history museum , chm

SoC and IP

50 Years of Turning Optical Dreams into Reality

Anaheim Convention Center (CA) was the center of a spectacle of technology that continues…

• 3 min read
Optical , PCIe Gen4 , OFC , Fiber , PCIe

Breakfast Bytes

Ann Winblad Masterclass

Normally the Stanford VLAB meets in Menlo Park, but occasionally they make a foray…

• 5 min read
ann winblad , vlab , hummer winblad , venture capital

Whiteboard Wednesdays

Whiteboard Wednesdays - The Future of Neural Networks

In this week's Whiteboard Wednesdays video, Chris Rowen looks at the future of neural…

• less than a min read
Whiteboard Wednesdays , IP , Chris Rowen , Tensilica , neural networks

Breakfast Bytes

Open Server Summit: How to Install 5,000 Servers Per Day

There are only a few end markets for semiconductors that really drive the technology…

• 6 min read
Open Server Summit , servers , datacenter

Verification

Building Efficient Scoreboards

A “scoreboard” is a verification component that checks the data sent to the DUT against…

• 7 min read

Breakfast Bytes

"Interoperability is the Only Way to Prove Standards Compliance"

At the recent TSMC Technology Symposium, Cadence and Mellanox demonstrated multi…

• 3 min read
pcie 4.0 , data center , PHY , mellanox , PCIe , mobile , PCI Express

Breakfast Bytes

Memory in China: XMC

Yesterday I covered the first half of the CASPA meeting last Saturday about memory…

• 4 min read
China , Memory , xmc , NAND flash , 3d nand flash , DRAM , caspa , goldman sachs , ibs

Verification

RTL Signoff vs. Functional Signoff

The notion of signoff has many layers to it, both in terms of complexity but also…

• 4 min read
funtional verification , IMC , metric driven verification (MDV) , functional coverage , MDV , vManager

Breakfast Bytes

Memory, the Turning Point of Chinese Semiconductor Industry

I can't keep away from work. Saturday found me in the Cadence auditorium for the…

• 5 min read
China , Memory , xmc , NAND flash , 3d nand flash , DRAM , caspa , goldman sachs , ibs

Breakfast Bytes

TI and UI: Texas Instruments' Experience with the Common User Interface

Cadence's tools Genus, Innovus, and Tempus have a lot of functionality in common…

• 3 min read
Genus , Tempus , Joules , Voltus , Innovus , Bob Sussman , Texas Instruments , TI , Breakfast Bytes , common UI

Whiteboard Wednesdays

Whiteboard Wednesdays - Common Infrastructure Between Simulation VIP and Accelerated…

In this week's Whiteboard Wednesdays video, Arindam Guha discusses the common infrastructure…

• less than a min read
accelerated VIP , Verification IP , simulation VIP , simulation

Academic Network

Cadence Participates in 14 Spring Career Fairs

Rain or snow does not stop our Cadence employees from being the perfect brand ambassadors…

• 1 min read
university , Cadence Academic Network , campus recruitment , academia

System, PCB, & Package Design 

What's Good About the latest RF PCB? New capabilities in 16.6-2015!

The 16.6-2015 RF PCB release contains many new features and updates. Read on for…

• 4 min read
RF , Cadence Design Systems , 16.6 , SPB , Grzenia , Allegro

Breakfast Bytes

Qualcomm Looks to the Future: Steve Mollenkopf's CDNLive Keynote

Steve Mollenkopf, the CEO of Qualcomm Incorporated, gave one of the keynotes at CDNLive…

• 4 min read
mollenkopf , CDNLive , IoT , Qualcomm , Internet of Things , drone , mobile , Snapdragon , CDNLive Silicon Valley , ARM , datacenter , Breakfast Bytes
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