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Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso

SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

Another New Blog on e/Specman

Specmaniacs rejoice: there is a new blog centered around verification with e /Specman…

• less than a min read
IEEE 1647 , Specman , Functional Verification , e , OVMWorld

Verification

Industry Standard SystemC is What Designers Want

This past Monday saw not one HLS related announcement but two...this space is really…

• 2 min read
ANSI-C , C-to-Silicon , SystemC , HLS , System Design and Verification

Verification

Inside Cadence: Food for Charity & Freedom

Earlier today at the Cadence San Jose campus, a charity event was held off-cycle…

• 2 min read
Functional Verification , festival , Stars&Strikes , charity benefit

Digital Design

Flow? What Flow?

For EDA software, it seems that it takes just as much effort to develop a methodology…

• 1 min read
Foundation Flow , EDI system , encounter digital implementation system , Digital Implementation , design closure

System, PCB, & Package Design 

What's Good About USB 3.0? You Tell Me

I read a recent article (June 11, 2009) in EDN magazine - " USB 3.0: A simple Idea…

• 2 min read
USB 3.0 , PHY , PCB design

Verification

Demo: New Simulation Comparison Utility in Incisive Enterprise Simulator

When I first hired on as an AE at Cadence (eighteen years ago!), I realized how many…

• less than a min read
funtional verification , Functional Verification , simvision , Incisive , Incisive Enterprise Simulator (IES) , IES , verification , IES-XL

Analog/Custom Design

Things You Didn't Know About Virtuoso: Which Way Should I "Go"?

Just a short post this week, as I've been quite busy recording videos for some of…

• 2 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

DAC Virtual Platform Workshop

Back in early May, I wrote that it was Not Too Early to Start Thinking About DAC…

• 1 min read
DAC , virtual platform , embedded software , metric-driven verification

RF Engineering

Periodic Steady-State Analysis for DC-to-DC Converters

In " Spectre RF by any other name ...", a non-RF application for Spectre RF's periodic…

• 3 min read
DAC , shooting newton , Spectre RF , THD , DC-to-DC converters , RF design , pss , SFDR

Verification

Create a Sine Wave Generator Using SystemVerilog

Two capabilities in SystemVerilog allow for the creation of a module that can produce…

• 2 min read
SystemVerilog , AMS , Functional Verification , Incisive , Incisive Enterprise Simulator (IES) , IES , IES-XL

SoC and IP

DDR3 DRAMs Update in June 2009

Abstract: DDR3 DRAMs, after a long period of floundering about, wondering 'when they…

• 3 min read

Verification

Yikes - Synopsys is Following Me!

No, I'm not being paranoid -- Synopsys, my largest competitor, is literally following…

• 2 min read
Specman , Functional Verification , OVM , OVM e , Coverage-Driven Verification , CDV , e , Twitter , eRM

Verification

The Golden Age of Electronics

About a month ago I took my family to The Bakken Museum in Minneapolis, Minnesota…

• 4 min read
System Design and Verification , C-to-Silicon , PCI Express , ESL

Verification

Using Constraints to Pass Configuration Options in the Unit Hierarchy (Top-Down approach…

To allow for increased solvability, some constraints that were previously uni-directional…

• 4 min read
IEEE 1647 , IntelliGen , Specman , Functional Verification , e , team specman , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , AOP , IES-XL

Analog/Custom Design

Optimization Environment Enables Effective Reuse of Existing Design Modules

In order to complete a brand new design on time, it is an important factor to effectively…

• 1 min read
virtuoso layout migrate , optimization , Virtuoso , reuse , Custom IC Design

Verification

Xilinx SoC FPGAs Ideal Fit For OVM and MDV

Processor-based FPGAs represent 40% of all the design starts today and will rise…

• 1 min read
SystemVerilog , Functional Verification , OVM , Incisive , xilinx , MDV , IES , FPGA

System, PCB, & Package Design 

What's Good About an FPGA Co-Design Environment? - Watch The Video For Answers

Check out Hemant Shah - Product Marketing Director for Allegro PCB Products - highlighting…

• 1 min read
FPGA: ASIC Prototype , FPGA System Planner , FSP , PCB design

Analog/Custom Design

Things You Didn't Know About Virtuoso: RMB, OMG! ;-)

I apologize for the Internet slang in the title ( urbandictionary calls OMG "the…

• 2 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Digital Design

Cadence: Committed to DFM

On June 10, Cadence issued a press release that mentioned “…decreasing the level…

• 1 min read
Advanced Node , Mixed-Signal , encounter , Virtuoso , Manufacturability sign-off , Digital Implementation , DFM
CDNS - Fix Layout Hompage