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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

Sunday Brunch Video for 29th August 2021

https://youtu.be/kC1SNcAmVWg Made in Levi's Stadium (camera Gary Bengier) Monday…

• less than a min read
sunday brunch

Life at Cadence

Interns Share What Makes Cadence Special

During their time at Cadence, interns work alongside our team of passionate and brilliant…

• 3 min read
Interns , Culture , cadence , internship

Analog/Custom Design

Virtuosity: Have You Joined the Computational Fluid Dynamics Bandwagon Yet?

A guest blog to let you know about Cadence’s recent ventures into the world of Computational…

• 5 min read
CFD , Aerospace , Pointwise , Wind Study , Computational Fluid Dynamics , CFD Vision 2030 , Virtuosity , NUMECA , Omnis

Breakfast Bytes

August Update: Stevies, Sales, Mars, Hacking Hotels, and More

Can you believe that it's the last Friday in August already? So, time for another…

• 4 min read
van gogh , SIA , tesla , stevies , update , Mars

カスタムIC／ミックスシグナル

Virtuosity: Virtuoso ADE AssemblerとVirtuoso ADE Explorerのユーザビリティがさらに向上

アナログ設計環境製品である Virtuoso ADE Assembler と Virtuoso ADE Explorer の最近のリリースでは、ユーザビリティの向上に努めてきました…

• less than a min read
Analog Design Environment , ADE Explorer , designing analog circuits , make editable , run point selection , ADE , variables , Virtuoso Analog Design Environment , analog integrated circuit design , make read-only , analog design , usability , japanese blog , Custom IC Design , ADE Assembler

Breakfast Bytes

A History of Timing Signoff

Today, when all timing signoff is done using static timing analysis with a tool such…

• 5 min read
Tempus , STA , static timing , gate level simulation

RF /マイクロ波設計

uWaveRiders:Cadence AWR Design Environmentに統合されたトランスミッションライン計算器

Team RF "μWaveRiders" ブログシリーズはCadence AWR RF製品のためのショーケースです。月ごとの話題はCadence AWR Design…

• less than a min read
Transmission Line Synthesis , RF Simulation , Circuit simulation , AWR Design Environment , Transmission Line Calculator , RF design , microwave office , japanese blog

中文技术专区

用自动化工作流程快速精准地实现刚柔结合电路板的 EM 分析

刊登于：actMWJC 《微波杂志》 现代电子设备对数据传输速度和更小体积的需求与日俱增，不断推动柔性电路板的发展。刚柔结合印刷电路板（PCB）由刚性母板和柔性电路组成…

FormerMember • 1 min read
PCB , ECAD , MCAD , EM , Allegro , clarity

カスタムIC／ミックスシグナル

Spectre Tech Tips: Spectreのハイインピーダンスノードチェックの概要

回路チェックは、ハイインピーダンスノード、電源間のリークパス、タイミングエラー、電力の問題、接続の問題、急激なrise/fallといった、典型的な設計問題を解析することができます…

• less than a min read
spectre aps , dyn_floatdcpath , dyn_float_tran_stat , dyn_highz , highz , static_highz , Spectre , japanese blog , static checks , spectre x , Design Checks , floating node

System, PCB, & Package Design 

BoardSurfers: Training Insights: Creating and Applying Spacing Constraint Sets in…

When designing a PCB layout, all the constraints and design rules must be followed…

• 4 min read
17.4 , BoardSurfers , Constraint Manager , Layout , 17.4-2019 , Training Insights , Constraints , Allegro PCB Editor , Allegro

Analog/Custom Design

Virtuoso Meets Maxwell: How the Revamped Feature-Intensive Export Die GUI Empowers…

Die export has evolved and it’s time to introduce the new look and feel of the GUI…

• 5 min read
Transfer Area , die export , IO pads , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , die , pin numbering , ICADVM20.1 , Custom IC Design , Virtuoso Layout Suite EXL , shapes , bumps , VMM

Breakfast Bytes

"I'm Doing an Operating System, Just a Hobby, Won't Be Big and Professional"

30 years ago today, August 25, 1991, an unknown Finnish student sent out what has…

• 3 min read
git , linus torvalds , linux

Breakfast Bytes

HOT CHIPS: Esperanto's Dave Ditzel and 1000 Minions

At HOT CHIPS this morning, Dave Ditzel of Esperanto is presenting their latest chip…

• 5 min read
minion , risc-v , esperanto , maxion , hot chips

System, PCB, & Package Design 

IC Packagers: New Releases Are Full of New Stuff!

This marks our third and final look at the biggest new features in this major update…

• 6 min read
17.4 QIR3 , IC Packaging and SiP , APD , IC Packagers , Allegro Package Designer , 17.4-2019

中文技术专区

针对GPGPU设计，Cadence RTL到Signoff流程解密

近年来，随着GPU在通用计算领域的高速发展，逐渐将应用范围扩展到图形之外，例如人工智能、深度学习和自动驾驶。这些领域的特点要求GPU在并行处理海量数据的同时提供更高的访存速度和浮点运算能力…

FormerMember • less than a min read
Glitch power , GPGPU , OCV , 预测布局

System, PCB, & Package Design 

System Analysis Knowledge Bytes: Signal, Power, and Thermal Integrity using Layout…

The System Analysis Knowledge Bytes blog series explores the capabilities and potential…

• 4 min read
Celsius Thermal Solver , Help Menu , OptimizePI , Sigrity , Clarity 3D Solver , Layout Workbench , XtractIM , PowerDC , Systems Analysis , PowerSI

Breakfast Bytes

CadenceLIVE: Xilinx's Thunder-Bus

At CadenceLIVE Americas in June, Raghukul presented on Thunder-Bus, a low-latency…

• 2 min read
protium x2 , Protium , xilinx

SoC and IP

PCIe for Automotive - DesignCon/DriveWorld 2021

DesignCon 2021, Drive World Conference, and Embedded Systems Conference are a joint…

• 3 min read
CXL , Design IP , IP , featured , PCIe Gen4 , ip cores , PCI , PCIe PHY

Academic Network

Academic and Entrepreneur Tracks at CadenceLIVE Europe 2021

CadenceLIVE Europe 2021 will be hosted on October 19th. This year will be a virtual…

• 2 min read
Entrepreneur , Cadence Academic Network , Master Thesis Award , cadencelive
CDNS - Fix Layout Hompage