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Featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
Corporate 11 Dec 2025 • 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP(Verification IP:VIP)を発表しました。今回発表されたVIPは…

Cadence Japan
Cadence Japan 4 Dec 2025 • less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
Cadence Japan 1 Dec 2025 • 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
Corporate 21 Nov 2025 • 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

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Blog - Post List
Latest blogs

カスタムIC/ミックスシグナル

Virtuosity: 新しいアイダイアグラムの測定

Virtuoso® Visualization and Analysis のEye Diagram アシスタントを使用すると、アイダイアグラムを作成したり、マスクを追加したり…

Custom IC Japan 10 Jul 2020 • less than a min read
Eye Mask , Analog Design Environment , ViVa-XL , ADE Explorer , Explorer , ADE XL , ADE , eye diagram , ViVA , Virtuosity , japanese blog , Custom IC Design , ADE Assembler

Analog/Custom Design

Virtuosity: Usability Enhancements in the Chop Command of Virtuoso Layout Suite

The Chop command in Virtuoso Layout Suite has been enhanced to improve your productivity…

KomalJohar 10 Jul 2020 • 2 min read
ICADVM18.1 , Layout Suite , Virtuoso , layout editing chop , usability , Custom IC Design , IC6.1.8

System, PCB, & Package Design 

BoardSurfers: 17.4-2019 HotFix 007 for ECAD-MCAD Library Creator Is Now Availabl…

The Library Creator 17.4-2019 HotFix 007 update is now available. This time, the…

Sanjiv Bhatia 10 Jul 2020 • 1 min read
Library Creator , 17.4-2020 , 17.4-QIR1 , 17.4-2019 , ECAD-MCAD Library Creator , PCB design , Allegro PCB Editor , Allegro

Breakfast Bytes

There Is a Statue of Nikola Tesla in Palo Alto...with Free WiFi

Tesla is most famous these days as the name of a car company. But Nikola Tesla was…

Paul McLellan 10 Jul 2020 • 6 min read
anniversary , Nikola Tesla , tesla

Academic Network

Cadence Academic Network Welcomes AWR and EMX Users to Join Us!

At the beginning of 2020, Cadence made two big announcements, as part of the Intelligent…

Anton Klotz 9 Jul 2020 • 3 min read
integrand , Cadence Academic Network , awr , EMX , intelligent system design , university program

Breakfast Bytes

Photography with Computers

Yesterday, in my post Photography of Computers , I wrote about photographing computers…

Paul McLellan 9 Jul 2020 • 5 min read
video , photography , mobile , Smartphone

Digital Design

Want to Explore Third-Party DFT Insertion Process in Genus?

Are you concerned about the process to integrate third-party DFT insertion during…

Neha Joshi 8 Jul 2020 • less than a min read
scan , DFT , Logic Design , third-party

Breakfast Bytes

Photography of Computers

In the early days of computers, I think computers were generally just called "computers…

Paul McLellan 8 Jul 2020 • 7 min read
fugaku , summit , home computers , photography

Analog/Custom Design

Virtuosity: In the Line of Veri-Fire - Episode 1

Hi readers! Welcome to Veri-Fire, a blog series that helps you deep dive into Virtuoso…

Team ADE Verifier 7 Jul 2020 • 8 min read
verifier , Analog Design Environment , Cadence blogs , ICADVM18.1 , Analog Coverage , verification plan , analog , ADE , analog verification , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , Virtuosity , ADE Blog Series , FAQ , implementations , analog design , Custom IC Design , requirements , Custom IC , ADE Verifier , IC6.1.8 , Assembler , custom design technology , ADE Assembler , verification

System, PCB, & Package Design 

IC Packagers: Automating Your LVS Text Label Generation

If you are using Allegro Package Designer Plus with the Silicon Layout option to…

Tyler 7 Jul 2020 • 4 min read
17.4 , IC Packaging , Allegro Package Designer , 17.4-2019

Breakfast Bytes

How Do You Run One Architecture on Another?

You probably already heard that going forward some Macs are going to be running on…

Paul McLellan 7 Jul 2020 • 5 min read
Intel , Apple , dynamic translation , jit

Breakfast Bytes

Sunday Brunch Video for 5th July 2020

https://youtu.be/qimXaFAFh6w Made for July 4th (camera me) Monday: Yesterday Was…

Paul McLellan 5 Jul 2020 • less than a min read
sunday brunch

カスタムIC/ミックスシグナル

Virtuosity: Virtuoso ADE ユーザビリティ改善に関する最新情報

私たちの世界では、ユーザビリティとは、製品を使いやすくし、アクセスを簡単にし、視覚的に魅力的なものにすることです。私たちは製品の使い勝手を改善するため、絶え間なく努力します…

Custom IC Japan 2 Jul 2020 • 2 min read
ADE Explorer , Rapid Adoption Kit , ViVA , ADE Design Environment , Virtuosity , usability , japanese blog , Custom IC Design , ADE Assembler

Analog/Custom Design

Start Your Engines: The Blog-o-Meter Check

A summary of the blogs published in the Start Your Engines blog series.

Jommy 2 Jul 2020 • 2 min read
CLIPS , mixed signal design , Functional Verification , AMS Designer , Unified Netlister , AMSD Flex Mode , mixed-signal verification

Analog/Custom Design

Virtuosity: Good News for our Japanese Readers

In this blog, I’m going to share some great news for our Japanese readers. Let's…

Dishika Majumdar 2 Jul 2020 • 3 min read
Trunk generation , ICADVM18.1 , AMS Designer , VPR , layout XL , Virtuoso , Japanese blogs , Virtuosity , advanced nodes , ASMD Flex Mode , Virtuoso Layout Suite , Custom IC

定制IC芯片设计

Virtuosity:大小一样的乐高积木,能拼出大师级杰作吗?

您需要使用不同大小和类型的积木块,才能拼出大师级的乐高杰作,基于WSP的设计也是如此,它需要将具有不同WSSPDef周期的多个模式的布线区域拼接在一起。接下来,让我们一起来探讨如何实现这一目标…

KomalJohar 2 Jul 2020 • less than a min read
Chinese blog , ICADVM18.1 , cadence , WSP , Advanced Node , Local regions , Layout Suite , width spacing patterns , Layout , Virtuoso , Virtuosity , usability , Custom IC Design , ux , WSSPDef

Breakfast Bytes

July 4th: The Glorious Revolution

The Fourth of July is coming up. Cadence is closed for a four-day weekend, so this…

Paul McLellan 2 Jul 2020 • 8 min read
offtopic

Breakfast Bytes

Japanese Arm-Powered Supercomputer Takes the TOP500 Crown

Twice a year, around the middle of the year (that would be now) and around the end…

Paul McLellan 1 Jul 2020 • 4 min read
fugaku , top500 , ARM , supercomputer

Analog/Custom Design

Virtuoso IC6.1.8 ISR12 and ICADVM18.1 ISR12 Now Available

The IC6.1.8 ISR12 and ICADVM18.1 ISR12 production releases are now available for…

Virtuoso Release Team 1 Jul 2020 • 3 min read
Cadence blogs , ICADVM18.1 , ADE Explorer , EM Solver , Virtuoso RF Solution , IC Release Announcement blog , Virtuoso , IC Release Blog , Virtuoso Layout Suite EXL , Virtuoso Layout Suite , ADE Verifier , IC6.1.8 , ADE Assembler , Virtuoso Layout Suite XL
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CDNS - Fix Layout Hompage

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