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Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella
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Latest blogs

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog , AI

Computational Fluid Dynamics

Automate Results Analysis in Fidelity with Python-Based Recording

Key Points Enhanced Reproducibility: Scripting captures the complete post-processing…

• 1 min read
Python , Cadence Fidelity , Python API , Fidelity CFD

Digital Design

AI’m Always With You While Working

Artificial intelligence (AI) is not only just a buzzword today; it also helps us…

• 3 min read
ECO , conformal , Static timing analysis , DFT , online courses , Innovus Implementation System , Gate level simualtion , LEC , STA , Cadence Webinar , Cadence Online Support , Floorplanning , RTL-to-GDSII , verisium , Xcelium Logic Simulator , training , Logic Design , coverage analysis , RTL-to-GDSII FrontEnd , training bytes , RTL-to-GDSII BackEnd , Digital Implementation , implementation , Genus Synthesis Solution , ATPG , Synthesis , RTL Code , signoff , Placement , RTL design , Tempus Timing Signoff Solution , IR drop , vManager , Modus ATPG

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink , ECOC , Ultra Ethernet

SoC and IP

Accelerate Automotive System Design with Cadence AI-Driven DSPs

The automotive industry is on the brink of a transformative era powered by intelligence…

• 6 min read
Automotive , infotainment , autonomy , In-cabin sensing , lidar , Xtensa CPU , radar , Tensilica , vision , ADAS

Data Center

Join Us for Data Center Technologies at CadenceCONNECT Middle East 2025

The future of data center innovation is converging in Abu Dhabi! Following the success…

• 2 min read
data center , digital twin , cadenceconnect

Analog/Custom Design

Virtuoso Studio Refreshed for Modern Outlook

Our new AI-powered custom design solution, Virtuoso Studio, leverages our 30 years…

• 5 min read
Virtuoso , Custom IC Design

Corporate News

Danfoss Amplifies PCB Design with Cadence Allegro X AI

Danfoss is a Danish family-owned multinational company with a focus on sustainability…

• 1 min read
designed with cadence

Computational Fluid Dynamics

Join the CFD Track at CadenceCONNECT Middle East 2025

Join us for a deep dive into the future of computational fluid dynamics (CFD). Following…

• 2 min read
CFD , cadenceconnect , Aerospace and Defense

System, PCB, & Package Design 

Determining Effects on PDN Target Impedance Using Sigrity X

Ensuring a functional power distribution network (PDN) for chips, packages, and PCBs…

• 2 min read
PDN , Sigrity X , PCB design , Sigrity

SoC and IP

A Hybrid Subsystem Architecture to Elevate Edge AI

The world of artificial intelligence is moving beyond the cloud and into our everyday…

• 4 min read
controller IP , DSP , cadence , NeuroEdge 130 , IoT , Tensilica DSPs , SoC , ip cores , Tensilica , semiconductor IP , AICP

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI , post event insights

SoC and IP

From 12 Hours to 2: How AI Accelerates Automotive Quality Assurance

In the fast-paced world of Industry 4.0, quality assurance (QA) is no longer just…

• 2 min read
Automotive , Regression , Verisium Manager

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

• 4 min read
Edge AI , featured , Ambarella

SoC and IP

Ensuring End-to-End Traceability for Safety-Critical Applications

There is now a direct interface between the Midas Safety Platform and popular requirements…

• 4 min read
Requirement Management System , Safety Solution , DOORS , functional safety , RMS , Safety , Product Lifecycle Management , Safety Analysis , JIRA , Traceability , Jama , Polarion , PLM , Codebeamer , Safety Compliance

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Verification

Evolution of AMBA AXI Protocol: An Introduction to the Issue L Update

To gain a comprehensive understanding of AMBA® AXI Issue L (AXI-L) protocol update…

• 3 min read
AXI , Verification IP

Verification

An Introduction to AMBA CHI Chip-to-Chip (C2C) Protocol

As chip designs grow larger and more complex, they become increasingly difficult…

• 2 min read
C2C , multi-die , chip-chip , AMBA , CHI VIP , verification

System, PCB, & Package Design 

BoardSurfers: Training Insights: Upskill Engineers using PCB Editor Basic Course

Are you seeking an effective and proven method to onboard and upskill new engineers…

• 4 min read
PCB , PCB Layout and routing , Routing , Allegro X PCB Editor , APD , Constraint Manager , via , PCB design , Allegro PCB Editor , allegro x , Schematic , Allegro
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