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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Latest blogs

Spotlight Taiwan

Palladium Z2和Protium X2 雙重奏(Dynamic Duo)引擎系統、邁向驗證新時代 !

原文出處: Dynamic Duo 2: The Sequel 作者: Paul McLellan 有一個故事，可能是虛構的，關於一位編劇在好萊塢找人投資影片的故事…

• less than a min read
dynamic duo , prototyping , protium x2 , palladium z2 , FPGA prototyping , taiwanese blog , software development , firmware development

Computational Fluid Dynamics

This Week in CFD

This Week in CFD reached convergence long before I had exhausted the two-week backlog…

• less than a min read
CFD , Pointwise , Computational Fluid Dynamics

Breakfast Bytes

Evolving Maturity in Ransomware

I recently attended a Black Hat seminar titled The Evolving Maturity in Ransomware…

• 6 min read
security , ransomware , cybersecurity

カスタムIC／ミックスシグナル

Spectre Tech Tips: リークパスによる電流ホットスポットの検出

回路設計において、誤った接続が望ましくないリークパスを引き起こし、結果として電流のホットスポットとなる可能性があります。こういった電流のホットスポットはSpectre…

• less than a min read
Dynamic design checks , Spectre design checks , leakage path detection , Spectre , dyn_dcpath , japanese blog , dyn_subcktpwr

Computational Fluid Dynamics

AeroDelft Pushes the Airline Industry towards a Sustainable Future with Liquid Hydrogen…

AeroDelft is a student team at the forefront of sustainable aviation. While based…

• less than a min read
CFD , Computational Fluid Dynamics

Breakfast Bytes

Programming Early Computers Was Very Different from Today

In my post "I Couldn't Imagine Being Too Poor for Servants, or Rich Enough for a…

• 10 min read
ibm 1130 , atlas II , icl 1904 , ict 1904 , history

Digital Design

Verifying Design Changes Does Not Have to be Difficult and Tedious — Make it Easier…

You put your design through a multitude of tools for various transformations. Going…

FormerMember • less than a min read
conformal , formal , Logic Design , Equivalence Checking , Digital Implementation , verification

Breakfast Bytes

Benedict Evans on Tech 2021: Harder Problems and Regulation

This is a continuation of last week's post Benedict Evans' on Tech in 2021 . That…

• 6 min read
benedict evans , Internet , regulation

SoC and IP

First Look: Cadence Subsystem SoC for PCIe 5.0

If a picture is worth a thousand words, a video tells you the entire story. Cadence…

• 1 min read
controller IP , CXL , PCI Express 5.0 , Design IP , IP , PHY , Gen5 , PCIe , semiconductor IP , Design and Verification IP , SerDes , Compute Express Link , SerDes IP , PCI Express

定制IC芯片设计

Virtuoso Video Diary: “Training bytes” 助推知识传播—第4部分

我们生活在一个日趋复杂的世界中，尽可能的使用和组合各种工具及平台，以及其它的可用功能，这对于我们而言至关重要. 在此博客中， 我们将介绍如何使用Spectre Simulation…

• 2 min read
Chinese blog , Virtuoso , Spectre , Online Support

System, PCB, & Package Design 

BoardSurfers: Training Insights: Setting Up and Using Pin Delays in Constraint M…

Pin delays are used to specify the time delay or length from the internal package…

• 2 min read
17.4 , cadence , BoardSurfers , Cadence Online Support , Constraint Manager , 17.4-2019 , Training Insights , Allegro PCB Editor

System, PCB, & Package Design 

Sigrity and Systems Analysis 2021.1 HF1 Release Now Available

The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2021.1 HF1 release is now available…

• 4 min read
Sigrity and Systems Analysis , Celsius Thermal Solver , Simplified Model , 2D Probes , External Heat Sink , ECXML Export , BNP Viewer , 3D Probes , Clarity 3D Solver , Clarity 3D Workbench , DC Refinement , Cloud Simulation

Breakfast Bytes

NUMECA, Computational Fluid Dynamics...and the America's Cup

What is computational fluid dynamics, or CFD? And what does that have to do with…

• 6 min read
CFD , Computational Fluid Dynamics , america's cup , NUMECA

SoC and IP

Taking the Wraps Off: Cadence IP Subsystem for PCIe 5.0

Cadence was the first IP provider to bring controllers for PCI Express (PCIe) 3.0…

• 2 min read
controller IP , CXL , PCI Express 5.0 , Design IP , IP , PHY , Gen5 , PCIe , semiconductor IP , Design IP and Verification IP , SerDes , Compute Express Link , SerDes IP , PCI , PCI Express

Breakfast Bytes

"Targeting" the Open Compute Project

Target (yes, that Target, the retailer) has an infrastructure and cloud conference…

• 3 min read
open compute project , OCP

Breakfast Bytes

Sunday Brunch Video for 11th April 2021

https://youtu.be/D29rGqkkf80 Made in "Hawaii" (camera Ziyue Zhang) Monday: Dynamic…

• less than a min read
sunday brunch

Breakfast Bytes

Have You Heard of ISO 21434? You Will

You probably already know what ISO 26262 is. If you don't, then you can find out…

• 4 min read
Automotive , iso 21434 , ISO 26262

PCB設計／ICパッケージ設計

Allegro System Capture のやり方で設計する

ロジック設計エンジニアのためのシリーズ 洗練された新しい設計エコシステム、Allegro® System Captureの世界へようこそ。この ASCENT シリーズでは…

• less than a min read
17.4 , 17.4-2019 , Allegro System Capture , japanese blog

Analog/Custom Design

Virtuoso Video Diary: Knowledge Booster - 5G mmWave Handset System Design

In this blog we would like to let you know – amongst other things - how to implement…

• 3 min read
training , Cadence training , digital badges , training bytes , Virtuoso , Cadence certified , Virtuoso Video Diary , Custom IC Design , online training , Custom IC
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