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Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella
cdns - all_blogs_categories

Blog - Post List

Latest blogs

System, PCB, & Package Design 

BoardSurfers: PCB Electronics—Six Tasks to Prepare Board for Manufacturing

You have placed components and routed the board. You are finally ready to send the…

• 5 min read
PCB Editor

Breakfast Bytes

Open Source in 2020

I recently wrote a couple of posts about open-source EDA tools, OpenROAD: Open-Source…

• 9 min read
open source eda , open source

Breakfast Bytes

Protium and Palladium 1st=

We just finished 2019, of course, so it is time for annual "Best of 2019" lists.…

• 5 min read
Protium , Palladium , embedded software , Emulation

Breakfast Bytes

The History of Lithography, Part 2: From Double-Patterning to EUV

This is a continuation of yesterday's post The History of Lithography, Part 1: From…

• 8 min read
asml , lithography , Double Patterning , multi-patterning , EUV

Breakfast Bytes

The History of Lithography, Part 1: From Stones to Lasers

Lithography was originally a way of printing using a flat stone. Lithos (or λίθος…

• 7 min read
lithography , 193i , RET

The India Circuit

2019: The Year That Was...And Some Surprising News

The biggest happening in 2019 for India was, of course, the general elections. (Though…

• 3 min read
5G , artificial intelligence , deep learning , 2019 , Deep Tech , AI

System, PCB, & Package Design 

The Year That Was: PCB Design Blogs in 2019

The first series BoardSurfers is about PCB designing. It provides information on…

• 2 min read
Library and design data management , PCB Editor , 17.4-2019 , PCB design

System, PCB, & Package Design 

IC Packagers: Stepping into 2020

We started 2019 with the promise to cover all the topics that might interest you…

• 2 min read
Allegro Package Designer

System, PCB, & Package Design 

IC Packagers: Routing Clean-Up Prior to Manufacturing

A fantastic year is ending, so I want to take a quick opportunity to go over some…

• 5 min read
Allegro Package Designer

System, PCB, & Package Design 

IC Packagers: Guiding Your Team with Workflows

The flow for efficiently and correctly designing a package substrate layout is a…

• 5 min read
APD

Breakfast Bytes

Sunday Brunch Video for 22nd December 2019

https://youtu.be/iEuzyt_6O_A Made in my living room (camera Carey Guo) Monday: The…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

如何利用Allegro SiP Layout工具5步实现复杂引线框架封装的完整设计？

文章翻译自Cadence博客“ Designing a Complex Leadframe Package? See How SiP Layout Tool Can…

• less than a min read
Chinese blog , SiP , SiP设计 , 引线框架 , 中文 , 封装设计 , IC封装 , SiP Layout

Academic Network

Cadence Co-organized the First EDA Competition to Help China Train More EDA Tale…

The first “China IC and EDA Design Elite Competition” started in June 2019 and received…

• 2 min read
university , Cadence Academic Network , academia , EDA

Breakfast Bytes

Off-Topic: 2019 TV Anniversaries

It's the day before a holiday. Or in this case, ten days when Cadence will be shut…

• 6 min read
off-topic

Digital Design

Library Characterization Tidbits: A Matrix for Your Reference

When working on multiple tools of the Cadence Liberate Characterization Portfolio…

• 2 min read
parameter , Liberate AMS , Matrix , liberate blog , Liberate LV , Commands , Liberate Variety , Liberate MX , Liberate , Liberate Characterization Portfolio

Breakfast Bytes

IEDM 2019: An Overview...Plus the Future of EUV

IEDM, the International Electron Devices Meeting, took place last week. It was also…

• 6 min read
EUV , IEDM

Analog/Custom Design

Virtuosity: Looking Back at Virtuoso ADE Product Suite and Virtuoso Visualization…

2019 was quite an eventful year for Virtuoso  ADE Product Suite and Virtuoso  Visualization…

• 4 min read
ADE waveform window , Cadence blogs , ICADVM18.1 , ADE Explorer , virtuoso visualization and analysis , Virtuosity , Virtuoso Video Diary , Custom IC Design , ADE Verifier , IC6.1.8 , ADE Assembler

Digital Design

2019 Annual HLS Survey Results

Each year, we survey the industry to get an idea of the industry’s experiences and…

• 2 min read

Breakfast Bytes

System in Package? How to Plan and Build It

This is a follow on to my previous two pieces about system-in-package (SiP) designs…

• 3 min read
system in package , chiplet , 3DIC , OrbitIO
CDNS - Fix Layout Hompage