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Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

Digital Design

Power Tradeoffs for Chiplets: What Designers Need to Know

The rise of chiplets in advanced system design presents opportunities as well as…

• 3 min read
chiplets , Voltus IC Power Integrity Solution , Power Integrity

Corporate News

Unlocking Breakthroughs with Accelerated Compute

The future of system and electronic design is here—and it’s unprecedentedly fast…

• 6 min read
Protium , Palladium , accelerated compute , millennium

Verification

Evolution of CXL PBR Switch in the CXL Fabric

Compute Express Link (CXL) is a transformative technology that significantly improves…

• 5 min read
Fabric manager , Routing , switch , CXL3.0 , CXL switch , TYPE , SPID , PBR , DPID

Life at Cadence

Shaping the Future Through Experience

This summer, Cadence hosted five interns in partnership with Break Through Tech at…

• 2 min read
STEM , Work that matters , LifeAtCadence

SoC and IP

CNNs and Transformers: Decoding the Titans of AI

In the rapidly advancing field of artificial intelligence, two neural network architectures…

• 8 min read
IP , ip cores , Tensilica , SSG , semiconductor IP , AI

SoC and IP

From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success

Data rates are escalating with seemingly no end in sight due to the insatiable demand…

• 2 min read
DIP , ip validation , post silicon , full subsystem , verification

Corporate News

Alphawave Semi – Designing High-Speed Connectivity Solutions with Cadence Tools

Alphawave Semi designs high-speed connectivity solutions for customers in high-growth…

• 1 min read
celsius , designed with cadence , Sigrity , connectivity , clarity

Life at Cadence

Employee Spotlight: Engineering Excellence and Team Spirit at Cadence

Behind every milestone at Cadence is a team of passionate individuals who bring energy…

• 1 min read
Cadence Culture , LifeAtCadence

Verification

UEC-CBFC: Credit-Based Flow Control for Next-Gen Ethernet in AI and HPC

For ages, Ethernet has been the backbone of networking — starting from simple web…

• 2 min read
Verification IP , artificial intelligence , Ethernet VIP , Functional Verification , VIP , UEC , machine learning , Ethernet , Hyperscalers

Digital Design

Clock Tree Synthesis (CTS): The Backbone of Physical Design

In the intricate world of digital design, timing is everything. At the heart of this…

• 4 min read
EDI , online courses , HT Algorithme , STA , Cadence Online Support , training , Logic Design , training bytes , clock tree synthesis , Digital Implementation , Innovus , SDC , skew , online training , clock gating

Digital Design

EDA Unplugged: The Behind-The-Scenes Bloopers of Chip Design

Welcome to the binge-worthy series you didn't know you needed—"EDA: Silicon, Security…

• 4 min read
videos , online courses , Electronic Design Automation , training bytes , Semiconductor , online training

Life at Cadence

Uniting Innovators: CIC 2025 Showcases Cadence’s One Team Culture

What happens when 500 Cadence employees from 22 countries come together to share…

• 6 min read
innovation , Cadence Culture

Verification

Training Insight: Unlocking the Power of the Xcelium Logic Simulator

In the fast-paced world of digital design and verification, simulation tools are…

• 1 min read
Xcelium Logic Simulator , Training Insights

Analog/Custom Design

Spectre 25.1 Release Now Available

The SPECTRE 25.1 release is now available for download at Cadence Downloads. For…

• 1 min read
featured , Spectre FMC Analysis , Spectre RF , Spectre Photonics , Spectre AMS Designer , Spectre , Spectre Fast Monte Carlo , Spectre X Simulator

Verification

Fast Emulation Requires Fast Debug! This Is How It is Done

Introduction Emulation has become a critical tool for verifying complex system-on…

• 3 min read
debug , Palladium , verisium , Emulation , Verisium Debug

Verification

Scalable I/O Virtualization: A Deep Dive into PCIe’s Next Gen Virtualization

The demands of modern cloud computing—massive scale, constant agility, and tight…

• 6 min read
Verification IP , Functional Verification , VIP , PCIe

SoC and IP

Next-Gen Memory Starts Here: Cadence at the Future of Memory and Storage

FMS: the Future of Memory and Storage is fast approaching (August 5-7 at the Santa…

• 2 min read
ddr5 , Design IP , Memory , FMS , PCIe , SerDes , UALink

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Verification

LPDDR6: The Next-Generation LPDDR Device Standard and How It Differs from LPDDR5

Low-power DDR SDRAM has been one of the most widely used memories in the semiconductor…

• 4 min read
Verification IP , LOW POWER DRAM , JEDEC , LPDDR6 Vs LPDDR5 , DRAM , lpddr5 , lpddr5x , memory models , Lpddr6
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